SuperTuxKart 1.5 upstream source (from official release tarball)
This commit is contained in:
Benjamin
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/* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Copyright:
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* 2021 Evan Nemerson <evan@nemerson.com>
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*/
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#if !defined(SIMDE_ARM_SVE_CMPLT_H)
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#define SIMDE_ARM_SVE_CMPLT_H
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#include "types.h"
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HEDLEY_DIAGNOSTIC_PUSH
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SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
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SIMDE_FUNCTION_ATTRIBUTES
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simde_svbool_t
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simde_svcmplt_s8(simde_svbool_t pg, simde_svint8_t op1, simde_svint8_t op2) {
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#if defined(SIMDE_ARM_SVE_NATIVE)
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return svcmplt_s8(pg, op1, op2);
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#else
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simde_svbool_t r;
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#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
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&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
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r = simde_svbool_from_mmask64(_mm512_mask_cmplt_epi8_mask(simde_svbool_to_mmask64(pg), op1.m512i, op2.m512i));
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#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
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&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
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r = simde_svbool_from_mmask32(_mm256_mask_cmplt_epi8_mask(simde_svbool_to_mmask32(pg), op1.m256i[0], op2.m256i[0]));
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#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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r.neon_i8 = vandq_s8(pg.neon_i8, vreinterpretq_s8_u8(vcltq_s8(op1.neon, op2.neon)));
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#elif defined(SIMDE_X86_SSE2_NATIVE)
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for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
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r.m128i[i] = _mm_and_si128(pg.m128i[i], _mm_cmplt_epi8(op1.m128i[i], op2.m128i[i]));
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}
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#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
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r.altivec_b8 = vec_and(pg.altivec_b8, vec_cmplt(op1.altivec, op2.altivec));
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#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
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r.altivec_b8 = pg.altivec_b8 & vec_cmplt(op1.altivec, op2.altivec);
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#elif defined(SIMDE_WASM_SIMD128_NATIVE)
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r.v128 = wasm_v128_and(pg.v128, wasm_i8x16_lt(op1.v128, op2.v128));
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#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
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r.values_i8 = pg.values_i8 & HEDLEY_REINTERPRET_CAST(__typeof__(r.values_i8), op1.values < op2.values);
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#else
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SIMDE_VECTORIZE
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for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values_i8) / sizeof(r.values_i8[0])) ; i++) {
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r.values_i8[i] = pg.values_i8[i] & ((op1.values[i] < op2.values[i]) ? ~INT8_C(0) : INT8_C(0));
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}
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#endif
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return r;
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#endif
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}
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#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
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#undef simde_svcmplt_s8
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#define svcmplt_s8(pg, op1, op2) simde_svcmplt_s8(pg, op1, op2)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_svbool_t
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simde_svcmplt_s16(simde_svbool_t pg, simde_svint16_t op1, simde_svint16_t op2) {
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#if defined(SIMDE_ARM_SVE_NATIVE)
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return svcmplt_s16(pg, op1, op2);
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#else
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simde_svbool_t r;
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#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
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&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
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r = simde_svbool_from_mmask32(_mm512_mask_cmplt_epi16_mask(simde_svbool_to_mmask32(pg), op1.m512i, op2.m512i));
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#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
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&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
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r = simde_svbool_from_mmask16(_mm256_mask_cmplt_epi16_mask(simde_svbool_to_mmask16(pg), op1.m256i[0], op2.m256i[0]));
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#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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r.neon_i16 = vandq_s16(pg.neon_i16, vreinterpretq_s16_u16(vcltq_s16(op1.neon, op2.neon)));
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#elif defined(SIMDE_X86_SSE2_NATIVE)
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for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
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r.m128i[i] = _mm_and_si128(pg.m128i[i], _mm_cmplt_epi16(op1.m128i[i], op2.m128i[i]));
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}
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#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
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r.altivec_b16 = vec_and(pg.altivec_b16, vec_cmplt(op1.altivec, op2.altivec));
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#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
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r.altivec_b16 = pg.altivec_b16 & vec_cmplt(op1.altivec, op2.altivec);
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#elif defined(SIMDE_WASM_SIMD128_NATIVE)
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r.v128 = wasm_v128_and(pg.v128, wasm_i16x8_lt(op1.v128, op2.v128));
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#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
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r.values_i16 = pg.values_i16 & HEDLEY_REINTERPRET_CAST(__typeof__(r.values_i16), op1.values < op2.values);
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#else
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SIMDE_VECTORIZE
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for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values_i16) / sizeof(r.values_i16[0])) ; i++) {
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r.values_i16[i] = pg.values_i16[i] & ((op1.values[i] < op2.values[i]) ? ~INT16_C(0) : INT16_C(0));
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}
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#endif
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return r;
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#endif
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}
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#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
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#undef simde_svcmplt_s16
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#define svcmplt_s16(pg, op1, op2) simde_svcmplt_s16(pg, op1, op2)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_svbool_t
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simde_svcmplt_s32(simde_svbool_t pg, simde_svint32_t op1, simde_svint32_t op2) {
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#if defined(SIMDE_ARM_SVE_NATIVE)
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return svcmplt_s32(pg, op1, op2);
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#else
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simde_svbool_t r;
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#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
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&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
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r = simde_svbool_from_mmask16(_mm512_mask_cmplt_epi32_mask(simde_svbool_to_mmask16(pg), op1.m512i, op2.m512i));
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#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
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&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
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r = simde_svbool_from_mmask8(_mm256_mask_cmplt_epi32_mask(simde_svbool_to_mmask8(pg), op1.m256i[0], op2.m256i[0]));
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#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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r.neon_i32 = vandq_s32(pg.neon_i32, vreinterpretq_s32_u32(vcltq_s32(op1.neon, op2.neon)));
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#elif defined(SIMDE_X86_SSE2_NATIVE)
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for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
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r.m128i[i] = _mm_and_si128(pg.m128i[i], _mm_cmplt_epi32(op1.m128i[i], op2.m128i[i]));
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}
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#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
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r.altivec_b32 = vec_and(pg.altivec_b32, vec_cmplt(op1.altivec, op2.altivec));
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#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
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r.altivec_b32 = pg.altivec_b32 & vec_cmplt(op1.altivec, op2.altivec);
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#elif defined(SIMDE_WASM_SIMD128_NATIVE)
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r.v128 = wasm_v128_and(pg.v128, wasm_i32x4_lt(op1.v128, op2.v128));
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#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
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r.values_i32 = pg.values_i32 & HEDLEY_REINTERPRET_CAST(__typeof__(r.values_i32), op1.values < op2.values);
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#else
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SIMDE_VECTORIZE
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for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values_i32) / sizeof(r.values_i32[0])) ; i++) {
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r.values_i32[i] = pg.values_i32[i] & ((op1.values[i] < op2.values[i]) ? ~INT32_C(0) : INT32_C(0));
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}
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#endif
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return r;
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#endif
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}
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#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
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#undef simde_svcmplt_s32
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#define svcmplt_s32(pg, op1, op2) simde_svcmplt_s32(pg, op1, op2)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_svbool_t
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simde_svcmplt_s64(simde_svbool_t pg, simde_svint64_t op1, simde_svint64_t op2) {
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#if defined(SIMDE_ARM_SVE_NATIVE)
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return svcmplt_s64(pg, op1, op2);
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#else
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simde_svbool_t r;
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#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
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&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
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r = simde_svbool_from_mmask8(_mm512_mask_cmplt_epi64_mask(simde_svbool_to_mmask8(pg), op1.m512i, op2.m512i));
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#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
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&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
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r = simde_svbool_from_mmask4(_mm256_mask_cmplt_epi64_mask(simde_svbool_to_mmask4(pg), op1.m256i[0], op2.m256i[0]));
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#elif defined(SIMDE_ARM_NEON_A64V8_NATIVE)
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r.neon_i64 = vandq_s64(pg.neon_i64, vreinterpretq_s64_u64(vcltq_s64(op1.neon, op2.neon)));
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#elif defined(SIMDE_POWER_ALTIVEC_P8_NATIVE)
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r.altivec_b64 = vec_and(pg.altivec_b64, vec_cmplt(op1.altivec, op2.altivec));
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#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
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r.altivec_b64 = pg.altivec_b64 & vec_cmplt(op1.altivec, op2.altivec);
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#elif defined(SIMDE_WASM_SIMD128_NATIVE) && defined(SIMDE_WASM_TODO)
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r.v128 = wasm_v128_and(pg.v128, wasm_i64x2_lt(op1.v128, op2.v128));
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#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
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r.values_i64 = pg.values_i64 & HEDLEY_REINTERPRET_CAST(__typeof__(r.values_i64), op1.values < op2.values);
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#else
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SIMDE_VECTORIZE
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for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values_i64) / sizeof(r.values_i64[0])) ; i++) {
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r.values_i64[i] = pg.values_i64[i] & ((op1.values[i] < op2.values[i]) ? ~INT64_C(0) : INT64_C(0));
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}
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#endif
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return r;
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#endif
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}
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#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
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#undef simde_svcmplt_s64
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#define svcmplt_s64(pg, op1, op2) simde_svcmplt_s64(pg, op1, op2)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_svbool_t
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simde_svcmplt_u8(simde_svbool_t pg, simde_svuint8_t op1, simde_svuint8_t op2) {
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#if defined(SIMDE_ARM_SVE_NATIVE)
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return svcmplt_u8(pg, op1, op2);
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#else
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simde_svbool_t r;
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#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
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&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
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r = simde_svbool_from_mmask64(_mm512_mask_cmplt_epu8_mask(simde_svbool_to_mmask64(pg), op1.m512i, op2.m512i));
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#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
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&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
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r = simde_svbool_from_mmask32(_mm256_mask_cmplt_epu8_mask(simde_svbool_to_mmask32(pg), op1.m256i[0], op2.m256i[0]));
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#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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r.neon_u8 = vandq_u8(pg.neon_u8, vcltq_u8(op1.neon, op2.neon));
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#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
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r.altivec_b8 = vec_and(pg.altivec_b8, vec_cmplt(op1.altivec, op2.altivec));
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#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
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r.altivec_b8 = pg.altivec_b8 & vec_cmplt(op1.altivec, op2.altivec);
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#elif defined(SIMDE_WASM_SIMD128_NATIVE)
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r.v128 = wasm_v128_and(pg.v128, wasm_u8x16_lt(op1.v128, op2.v128));
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#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
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r.values_u8 = pg.values_u8 & HEDLEY_REINTERPRET_CAST(__typeof__(r.values_u8), op1.values < op2.values);
|
||||
#else
|
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SIMDE_VECTORIZE
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for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values_u8) / sizeof(r.values_u8[0])) ; i++) {
|
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r.values_u8[i] = pg.values_u8[i] & ((op1.values[i] < op2.values[i]) ? ~UINT8_C(0) : UINT8_C(0));
|
||||
}
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||||
#endif
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||||
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return r;
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#endif
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||||
}
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#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
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||||
#undef simde_svcmplt_u8
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||||
#define svcmplt_u8(pg, op1, op2) simde_svcmplt_u8(pg, op1, op2)
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#endif
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||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svcmplt_u16(simde_svbool_t pg, simde_svuint16_t op1, simde_svuint16_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svcmplt_u16(pg, op1, op2);
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||||
#else
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||||
simde_svbool_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r = simde_svbool_from_mmask32(_mm512_mask_cmplt_epu16_mask(simde_svbool_to_mmask32(pg), op1.m512i, op2.m512i));
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r = simde_svbool_from_mmask16(_mm256_mask_cmplt_epu16_mask(simde_svbool_to_mmask16(pg), op1.m256i[0], op2.m256i[0]));
|
||||
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon_u16 = vandq_u16(pg.neon_u16, vcltq_u16(op1.neon, op2.neon));
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
|
||||
r.altivec_b16 = vec_and(pg.altivec_b16, vec_cmplt(op1.altivec, op2.altivec));
|
||||
#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec_b16 = pg.altivec_b16 & vec_cmplt(op1.altivec, op2.altivec);
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_v128_and(pg.v128, wasm_u16x8_lt(op1.v128, op2.v128));
|
||||
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
|
||||
r.values_u16 = pg.values_u16 & HEDLEY_REINTERPRET_CAST(__typeof__(r.values_u16), op1.values < op2.values);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values_u16) / sizeof(r.values_u16[0])) ; i++) {
|
||||
r.values_u16[i] = pg.values_u16[i] & ((op1.values[i] < op2.values[i]) ? ~UINT16_C(0) : UINT16_C(0));
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svcmplt_u16
|
||||
#define svcmplt_u16(pg, op1, op2) simde_svcmplt_u16(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svcmplt_u32(simde_svbool_t pg, simde_svuint32_t op1, simde_svuint32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svcmplt_u32(pg, op1, op2);
|
||||
#else
|
||||
simde_svbool_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r = simde_svbool_from_mmask16(_mm512_mask_cmplt_epu32_mask(simde_svbool_to_mmask16(pg), op1.m512i, op2.m512i));
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r = simde_svbool_from_mmask8(_mm256_mask_cmplt_epu32_mask(simde_svbool_to_mmask8(pg), op1.m256i[0], op2.m256i[0]));
|
||||
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon_u32 = vandq_u32(pg.neon_u32, vcltq_u32(op1.neon, op2.neon));
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
|
||||
r.altivec_b32 = vec_and(pg.altivec_b32, vec_cmplt(op1.altivec, op2.altivec));
|
||||
#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec_b32 = pg.altivec_b32 & vec_cmplt(op1.altivec, op2.altivec);
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_v128_and(pg.v128, wasm_u32x4_lt(op1.v128, op2.v128));
|
||||
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
|
||||
r.values_u32 = pg.values_u32 & HEDLEY_REINTERPRET_CAST(__typeof__(r.values_u32), op1.values < op2.values);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values_u32) / sizeof(r.values_u32[0])) ; i++) {
|
||||
r.values_u32[i] = pg.values_u32[i] & ((op1.values[i] < op2.values[i]) ? ~UINT32_C(0) : UINT32_C(0));
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svcmplt_u32
|
||||
#define svcmplt_u32(pg, op1, op2) simde_svcmplt_u32(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svcmplt_u64(simde_svbool_t pg, simde_svuint64_t op1, simde_svuint64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svcmplt_u64(pg, op1, op2);
|
||||
#else
|
||||
simde_svbool_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r = simde_svbool_from_mmask8(_mm512_mask_cmplt_epu64_mask(simde_svbool_to_mmask8(pg), op1.m512i, op2.m512i));
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r = simde_svbool_from_mmask4(_mm256_mask_cmplt_epu64_mask(simde_svbool_to_mmask4(pg), op1.m256i[0], op2.m256i[0]));
|
||||
#elif defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
r.neon_u64 = vandq_u64(pg.neon_u64, vcltq_u64(op1.neon, op2.neon));
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P8_NATIVE)
|
||||
r.altivec_b64 = vec_and(pg.altivec_b64, vec_cmplt(op1.altivec, op2.altivec));
|
||||
#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec_b64 = pg.altivec_b64 & vec_cmplt(op1.altivec, op2.altivec);
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE) && defined(SIMDE_WASM_TODO)
|
||||
r.v128 = wasm_v128_and(pg.v128, wasm_u64x2_lt(op1.v128, op2.v128));
|
||||
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
|
||||
r.values_u64 = pg.values_u64 & HEDLEY_REINTERPRET_CAST(__typeof__(r.values_u64), op1.values < op2.values);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values_u64) / sizeof(r.values_u64[0])) ; i++) {
|
||||
r.values_u64[i] = pg.values_u64[i] & ((op1.values[i] < op2.values[i]) ? ~UINT64_C(0) : UINT64_C(0));
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svcmplt_u64
|
||||
#define svcmplt_u64(pg, op1, op2) simde_svcmplt_u64(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svcmplt_f32(simde_svbool_t pg, simde_svfloat32_t op1, simde_svfloat32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svcmplt_f32(pg, op1, op2);
|
||||
#else
|
||||
simde_svbool_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r = simde_svbool_from_mmask16(_mm512_mask_cmp_ps_mask(simde_svbool_to_mmask16(pg), op1.m512, op2.m512, _CMP_LT_OQ));
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r = simde_svbool_from_mmask8(_mm256_mask_cmp_ps_mask(simde_svbool_to_mmask8(pg), op1.m256[0], op2.m256[0], _CMP_LT_OQ));
|
||||
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon_u32 = vandq_u32(pg.neon_u32, vcltq_f32(op1.neon, op2.neon));
|
||||
#elif defined(SIMDE_X86_SSE2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_castps_si128(_mm_and_ps(_mm_castsi128_ps(pg.m128i[i]), _mm_cmplt_ps(op1.m128[i], op2.m128[i])));
|
||||
}
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
|
||||
r.altivec_b32 = vec_and(pg.altivec_b32, vec_cmplt(op1.altivec, op2.altivec));
|
||||
#elif defined(SIMDE_ZARCH_ZVECTOR_14_NATIVE)
|
||||
r.altivec_b32 = pg.altivec_b32 & vec_cmplt(op1.altivec, op2.altivec);
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_v128_and(pg.v128, wasm_f32x4_lt(op1.v128, op2.v128));
|
||||
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
|
||||
r.values_i32 = pg.values_i32 & HEDLEY_REINTERPRET_CAST(__typeof__(r.values_i32), op1.values < op2.values);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values_i32) / sizeof(r.values_i32[0])) ; i++) {
|
||||
r.values_i32[i] = pg.values_i32[i] & ((op1.values[i] < op2.values[i]) ? ~INT32_C(0) : INT32_C(0));
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svcmplt_f32
|
||||
#define svcmplt_f32(pg, op1, op2) simde_svcmplt_f32(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svcmplt_f64(simde_svbool_t pg, simde_svfloat64_t op1, simde_svfloat64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svcmplt_f64(pg, op1, op2);
|
||||
#else
|
||||
simde_svbool_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r = simde_svbool_from_mmask8(_mm512_mask_cmp_pd_mask(simde_svbool_to_mmask8(pg), op1.m512d, op2.m512d, _CMP_LT_OQ));
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r = simde_svbool_from_mmask4(_mm256_mask_cmp_pd_mask(simde_svbool_to_mmask4(pg), op1.m256d[0], op2.m256d[0], _CMP_LT_OQ));
|
||||
#elif defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
r.neon_u64 = vandq_u64(pg.neon_u64, vcltq_f64(op1.neon, op2.neon));
|
||||
#elif defined(SIMDE_X86_SSE2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_castpd_si128(_mm_and_pd(_mm_castsi128_pd(pg.m128i[i]), _mm_cmplt_pd(op1.m128d[i], op2.m128d[i])));
|
||||
}
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P7_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec_b64 = pg.altivec_b64 & vec_cmplt(op1.altivec, op2.altivec);
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE) && defined(SIMDE_WASM_TODO)
|
||||
r.v128 = wasm_v128_and(pg.v128, wasm_f64x2_lt(op1.v128, op2.v128));
|
||||
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
|
||||
r.values_i64 = pg.values_i64 & HEDLEY_REINTERPRET_CAST(__typeof__(r.values_i64), op1.values < op2.values);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values_i64) / sizeof(r.values_i64[0])) ; i++) {
|
||||
r.values_i64[i] = pg.values_i64[i] & ((op1.values[i] < op2.values[i]) ? ~INT64_C(0) : INT64_C(0));
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svcmplt_f64
|
||||
#define svcmplt_f64(pg, op1, op2) simde_svcmplt_f64(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svcmplt(simde_svbool_t pg, simde_svint8_t op1, simde_svint8_t op2) { return simde_svcmplt_s8(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svcmplt(simde_svbool_t pg, simde_svint16_t op1, simde_svint16_t op2) { return simde_svcmplt_s16(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svcmplt(simde_svbool_t pg, simde_svint32_t op1, simde_svint32_t op2) { return simde_svcmplt_s32(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svcmplt(simde_svbool_t pg, simde_svint64_t op1, simde_svint64_t op2) { return simde_svcmplt_s64(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svcmplt(simde_svbool_t pg, simde_svuint8_t op1, simde_svuint8_t op2) { return simde_svcmplt_u8(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svcmplt(simde_svbool_t pg, simde_svuint16_t op1, simde_svuint16_t op2) { return simde_svcmplt_u16(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svcmplt(simde_svbool_t pg, simde_svuint32_t op1, simde_svuint32_t op2) { return simde_svcmplt_u32(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svcmplt(simde_svbool_t pg, simde_svuint64_t op1, simde_svuint64_t op2) { return simde_svcmplt_u64(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svcmplt(simde_svbool_t pg, simde_svfloat32_t op1, simde_svfloat32_t op2) { return simde_svcmplt_f32(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svcmplt(simde_svbool_t pg, simde_svfloat64_t op1, simde_svfloat64_t op2) { return simde_svcmplt_f64(pg, op1, op2); }
|
||||
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
SIMDE_FUNCTION_ATTRIBUTES svbool_t svcmplt(svbool_t pg, svint8_t op1, svint8_t op2) { return svcmplt_s8(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES svbool_t svcmplt(svbool_t pg, svint16_t op1, svint16_t op2) { return svcmplt_s16(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES svbool_t svcmplt(svbool_t pg, svint32_t op1, svint32_t op2) { return svcmplt_s32(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES svbool_t svcmplt(svbool_t pg, svint64_t op1, svint64_t op2) { return svcmplt_s64(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES svbool_t svcmplt(svbool_t pg, svuint8_t op1, svuint8_t op2) { return svcmplt_u8(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES svbool_t svcmplt(svbool_t pg, svuint16_t op1, svuint16_t op2) { return svcmplt_u16(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES svbool_t svcmplt(svbool_t pg, svuint32_t op1, svuint32_t op2) { return svcmplt_u32(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES svbool_t svcmplt(svbool_t pg, svuint64_t op1, svuint64_t op2) { return svcmplt_u64(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES svbool_t svcmplt(svbool_t pg, svfloat32_t op1, svfloat32_t op2) { return svcmplt_f32(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES svbool_t svcmplt(svbool_t pg, svfloat64_t op1, svfloat64_t op2) { return svcmplt_f64(pg, op1, op2); }
|
||||
#endif
|
||||
#elif defined(SIMDE_GENERIC_)
|
||||
#define simde_svcmplt(pg, op1, op2) \
|
||||
(SIMDE_GENERIC_((op1), \
|
||||
simde_svint8_t: simde_svcmplt_s8)(pg, op1, op2), \
|
||||
simde_svint16_t: simde_svcmplt_s16)(pg, op1, op2), \
|
||||
simde_svint32_t: simde_svcmplt_s32)(pg, op1, op2), \
|
||||
simde_svint64_t: simde_svcmplt_s64)(pg, op1, op2), \
|
||||
simde_svuint8_t: simde_svcmplt_u8)(pg, op1, op2), \
|
||||
simde_svuint16_t: simde_svcmplt_u16)(pg, op1, op2), \
|
||||
simde_svuint32_t: simde_svcmplt_u32)(pg, op1, op2), \
|
||||
simde_svuint64_t: simde_svcmplt_u64)(pg, op1, op2), \
|
||||
simde_svint32_t: simde_svcmplt_f32)(pg, op1, op2), \
|
||||
simde_svint64_t: simde_svcmplt_f64)(pg, op1, op2))
|
||||
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#define svcmplt(pg, op1, op2) \
|
||||
(SIMDE_GENERIC_((op1), \
|
||||
svint8_t: svcmplt_s8)(pg, op1, op2), \
|
||||
svint16_t: svcmplt_s16)(pg, op1, op2), \
|
||||
svint32_t: svcmplt_s32)(pg, op1, op2), \
|
||||
svint64_t: svcmplt_s64)(pg, op1, op2), \
|
||||
svuint8_t: svcmplt_u8)(pg, op1, op2), \
|
||||
svuint16_t: svcmplt_u16)(pg, op1, op2), \
|
||||
svuint32_t: svcmplt_u32)(pg, op1, op2), \
|
||||
svuint64_t: svcmplt_u64)(pg, op1, op2), \
|
||||
svint32_t: svcmplt_f32)(pg, op1, op2), \
|
||||
svint64_t: svcmplt_f64)(pg, op1, op2))
|
||||
#endif
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef svcmplt
|
||||
#define svcmplt(pg, op1, op2) simde_svcmplt((pg), (op1), (op2))
|
||||
#endif
|
||||
|
||||
HEDLEY_DIAGNOSTIC_POP
|
||||
|
||||
#endif /* SIMDE_ARM_SVE_CMPLT_H */
|
||||
@@ -0,0 +1,93 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use, copy,
|
||||
* modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
* of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Copyright:
|
||||
* 2021 Evan Nemerson <evan@nemerson.com>
|
||||
*/
|
||||
|
||||
#if !defined(SIMDE_ARM_SVE_CNT_H)
|
||||
#define SIMDE_ARM_SVE_CNT_H
|
||||
|
||||
#include "types.h"
|
||||
|
||||
HEDLEY_DIAGNOSTIC_PUSH
|
||||
SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
uint64_t
|
||||
simde_svcntb(void) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svcntb();
|
||||
#else
|
||||
return sizeof(simde_svint8_t) / sizeof(int8_t);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svcntb
|
||||
#define svcntb() simde_svcntb()
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
uint64_t
|
||||
simde_svcnth(void) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svcnth();
|
||||
#else
|
||||
return sizeof(simde_svint16_t) / sizeof(int16_t);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svcnth
|
||||
#define svcnth() simde_svcnth()
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
uint64_t
|
||||
simde_svcntw(void) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svcntw();
|
||||
#else
|
||||
return sizeof(simde_svint32_t) / sizeof(int32_t);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svcntw
|
||||
#define svcntw() simde_svcntw()
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
uint64_t
|
||||
simde_svcntd(void) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svcntd();
|
||||
#else
|
||||
return sizeof(simde_svint64_t) / sizeof(int64_t);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svcntd
|
||||
#define svcntd() simde_svcntd()
|
||||
#endif
|
||||
|
||||
HEDLEY_DIAGNOSTIC_POP
|
||||
|
||||
#endif /* SIMDE_ARM_SVE_CNT_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,358 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use, copy,
|
||||
* modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
* of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Copyright:
|
||||
* 2021 Evan Nemerson <evan@nemerson.com>
|
||||
*/
|
||||
|
||||
/* Note: we don't have vector implementations for most of these because
|
||||
* we can't just load everything and mask out the uninteresting bits;
|
||||
* that might cause a fault, for example if the end of the buffer buts
|
||||
* up against a protected page.
|
||||
*
|
||||
* One thing we might be able to do would be to check if the predicate
|
||||
* is all ones and, if so, use an unpredicated load instruction. This
|
||||
* would probably we worthwhile for smaller types, though perhaps not
|
||||
* for larger types since it would mean branching for every load plus
|
||||
* the overhead of checking whether all bits are 1. */
|
||||
|
||||
#if !defined(SIMDE_ARM_SVE_LD1_H)
|
||||
#define SIMDE_ARM_SVE_LD1_H
|
||||
|
||||
#include "types.h"
|
||||
|
||||
HEDLEY_DIAGNOSTIC_PUSH
|
||||
SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint8_t
|
||||
simde_svld1_s8(simde_svbool_t pg, const int8_t * base) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svld1_s8(pg, base);
|
||||
#else
|
||||
simde_svint8_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_maskz_loadu_epi8(simde_svbool_to_mmask64(pg), base);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_maskz_loadu_epi8(simde_svbool_to_mmask32(pg), base);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntb()) ; i++) {
|
||||
r.values[i] = pg.values_i8[i] ? base[i] : INT8_C(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svld1_s8
|
||||
#define svld1_s8(pg, base) simde_svld1_s8((pg), (base))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint16_t
|
||||
simde_svld1_s16(simde_svbool_t pg, const int16_t * base) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svld1_s16(pg, base);
|
||||
#else
|
||||
simde_svint16_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_maskz_loadu_epi16(simde_svbool_to_mmask32(pg), base);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_maskz_loadu_epi16(simde_svbool_to_mmask16(pg), base);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcnth()) ; i++) {
|
||||
r.values[i] = pg.values_i16[i] ? base[i] : INT16_C(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svld1_s16
|
||||
#define svld1_s16(pg, base) simde_svld1_s16((pg), (base))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint32_t
|
||||
simde_svld1_s32(simde_svbool_t pg, const int32_t * base) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svld1_s32(pg, base);
|
||||
#else
|
||||
simde_svint32_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_maskz_loadu_epi32(simde_svbool_to_mmask16(pg), base);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_maskz_loadu_epi32(simde_svbool_to_mmask8(pg), base);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntw()) ; i++) {
|
||||
r.values[i] = pg.values_i32[i] ? base[i] : INT32_C(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svld1_s32
|
||||
#define svld1_s32(pg, base) simde_svld1_s32((pg), (base))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint64_t
|
||||
simde_svld1_s64(simde_svbool_t pg, const int64_t * base) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svld1_s64(pg, base);
|
||||
#else
|
||||
simde_svint64_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_maskz_loadu_epi64(simde_svbool_to_mmask8(pg), base);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_maskz_loadu_epi64(simde_svbool_to_mmask4(pg), base);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntd()) ; i++) {
|
||||
r.values[i] = pg.values_i64[i] ? base[i] : INT64_C(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svld1_s64
|
||||
#define svld1_s64(pg, base) simde_svld1_s64((pg), (base))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint8_t
|
||||
simde_svld1_u8(simde_svbool_t pg, const uint8_t * base) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svld1_u8(pg, base);
|
||||
#else
|
||||
simde_svuint8_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_maskz_loadu_epi8(simde_svbool_to_mmask64(pg), base);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_maskz_loadu_epi8(simde_svbool_to_mmask32(pg), base);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntb()) ; i++) {
|
||||
r.values[i] = pg.values_i8[i] ? base[i] : UINT8_C(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svld1_u8
|
||||
#define svld1_u8(pg, base) simde_svld1_u8((pg), (base))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint16_t
|
||||
simde_svld1_u16(simde_svbool_t pg, const uint16_t * base) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svld1_u16(pg, base);
|
||||
#else
|
||||
simde_svuint16_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_maskz_loadu_epi16(simde_svbool_to_mmask32(pg), base);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_maskz_loadu_epi16(simde_svbool_to_mmask16(pg), base);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcnth()) ; i++) {
|
||||
r.values[i] = pg.values_i16[i] ? base[i] : UINT16_C(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svld1_u16
|
||||
#define svld1_u16(pg, base) simde_svld1_u16((pg), (base))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint32_t
|
||||
simde_svld1_u32(simde_svbool_t pg, const uint32_t * base) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svld1_u32(pg, base);
|
||||
#else
|
||||
simde_svuint32_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_maskz_loadu_epi32(simde_svbool_to_mmask16(pg), base);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_maskz_loadu_epi32(simde_svbool_to_mmask8(pg), base);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntw()) ; i++) {
|
||||
r.values[i] = pg.values_i32[i] ? base[i] : UINT32_C(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svld1_u32
|
||||
#define svld1_u32(pg, base) simde_svld1_u32((pg), (base))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint64_t
|
||||
simde_svld1_u64(simde_svbool_t pg, const uint64_t * base) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svld1_u64(pg, base);
|
||||
#else
|
||||
simde_svuint64_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_maskz_loadu_epi64(simde_svbool_to_mmask8(pg), base);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_maskz_loadu_epi64(simde_svbool_to_mmask4(pg), base);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntd()) ; i++) {
|
||||
r.values[i] = pg.values_i64[i] ? base[i] : UINT64_C(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svld1_u64
|
||||
#define svld1_u64(pg, base) simde_svld1_u64((pg), (base))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svfloat32_t
|
||||
simde_svld1_f32(simde_svbool_t pg, const simde_float32 * base) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svld1_f32(pg, base);
|
||||
#else
|
||||
simde_svfloat32_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512 = _mm512_maskz_loadu_ps(simde_svbool_to_mmask16(pg), base);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256[0] = _mm256_maskz_loadu_ps(simde_svbool_to_mmask8(pg), base);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntw()) ; i++) {
|
||||
r.values[i] = pg.values_i32[i] ? base[i] : SIMDE_FLOAT32_C(0.0);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svld1_f32
|
||||
#define svld1_f32(pg, base) simde_svld1_f32((pg), (base))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svfloat64_t
|
||||
simde_svld1_f64(simde_svbool_t pg, const simde_float64 * base) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svld1_f64(pg, base);
|
||||
#else
|
||||
simde_svfloat64_t r;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512d = _mm512_maskz_loadu_pd(simde_svbool_to_mmask8(pg), base);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256d[0] = _mm256_maskz_loadu_pd(simde_svbool_to_mmask4(pg), base);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntd()) ; i++) {
|
||||
r.values[i] = pg.values_i64[i] ? base[i] : SIMDE_FLOAT64_C(0.0);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svld1_f64
|
||||
#define svld1_f64(pg, base) simde_svld1_f64((pg), (base))
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svld1(simde_svbool_t pg, const int8_t * base) { return simde_svld1_s8 (pg, base); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svld1(simde_svbool_t pg, const int16_t * base) { return simde_svld1_s16(pg, base); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svld1(simde_svbool_t pg, const int32_t * base) { return simde_svld1_s32(pg, base); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svld1(simde_svbool_t pg, const int64_t * base) { return simde_svld1_s64(pg, base); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svld1(simde_svbool_t pg, const uint8_t * base) { return simde_svld1_u8 (pg, base); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svld1(simde_svbool_t pg, const uint16_t * base) { return simde_svld1_u16(pg, base); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svld1(simde_svbool_t pg, const uint32_t * base) { return simde_svld1_u32(pg, base); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svld1(simde_svbool_t pg, const uint64_t * base) { return simde_svld1_u64(pg, base); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svld1(simde_svbool_t pg, const simde_float32 * base) { return simde_svld1_f32(pg, base); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svld1(simde_svbool_t pg, const simde_float64 * base) { return simde_svld1_f64(pg, base); }
|
||||
#elif defined(SIMDE_GENERIC_)
|
||||
#define simde_svld1(pg, base) \
|
||||
(SIMDE_GENERIC_((base), \
|
||||
const int8_t *: simde_svld1_s8 , \
|
||||
const int16_t *: simde_svld1_s16, \
|
||||
const int32_t *: simde_svld1_s32, \
|
||||
const int64_t *: simde_svld1_s64, \
|
||||
const uint8_t *: simde_svld1_u8 , \
|
||||
const uint16_t *: simde_svld1_u16, \
|
||||
const uint32_t *: simde_svld1_u32, \
|
||||
const uint64_t *: simde_svld1_u64, \
|
||||
const simde_float32 *: simde_svld1_f32, \
|
||||
const simde_float64 *: simde_svld1_f64)(pg, base))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef svld1
|
||||
#define svld1(pg, base) simde_svld1((pg), (base))
|
||||
#endif
|
||||
|
||||
HEDLEY_DIAGNOSTIC_POP
|
||||
|
||||
#endif /* SIMDE_ARM_SVE_LD1_H */
|
||||
@@ -0,0 +1,71 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use, copy,
|
||||
* modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
* of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Copyright:
|
||||
* 2021 Evan Nemerson <evan@nemerson.com>
|
||||
*/
|
||||
|
||||
#if !defined(SIMDE_ARM_SVE_PTEST_H)
|
||||
#define SIMDE_ARM_SVE_PTEST_H
|
||||
|
||||
#include "types.h"
|
||||
|
||||
HEDLEY_DIAGNOSTIC_PUSH
|
||||
SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_bool
|
||||
simde_svptest_first(simde_svbool_t pg, simde_svbool_t op) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svptest_first(pg, op);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_LIKELY(pg.value & 1))
|
||||
return op.value & 1;
|
||||
|
||||
if (pg.value == 0 || op.value == 0)
|
||||
return 0;
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
unsigned long r = 0;
|
||||
_BitScanForward64(&r, HEDLEY_STATIC_CAST(uint64_t, pg.value));
|
||||
return (op.value >> r) & 1;
|
||||
#else
|
||||
return (op.value >> __builtin_ctzll(HEDLEY_STATIC_CAST(unsigned long long, pg.value))) & 1;
|
||||
#endif
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntb()) ; i++) {
|
||||
if (pg.values_i8[i]) {
|
||||
return !!op.values_i8[i];
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svptest_first
|
||||
#define svptest_first(pg, op) simde_svptest_first(pg, op)
|
||||
#endif
|
||||
|
||||
HEDLEY_DIAGNOSTIC_POP
|
||||
|
||||
#endif /* SIMDE_ARM_SVE_PTEST_H */
|
||||
@@ -0,0 +1,157 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use, copy,
|
||||
* modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
* of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Copyright:
|
||||
* 2021 Evan Nemerson <evan@nemerson.com>
|
||||
*/
|
||||
|
||||
#if !defined(SIMDE_ARM_SVE_PTRUE_H)
|
||||
#define SIMDE_ARM_SVE_PTRUE_H
|
||||
|
||||
#include "types.h"
|
||||
|
||||
HEDLEY_DIAGNOSTIC_PUSH
|
||||
SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svptrue_b8(void) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svptrue_b8();
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
simde_svbool_t r;
|
||||
|
||||
#if SIMDE_ARM_SVE_VECTOR_SIZE >= 512
|
||||
r = simde_svbool_from_mmask64(HEDLEY_STATIC_CAST(__mmask64, ~UINT64_C(0)));
|
||||
#else
|
||||
r = simde_svbool_from_mmask32(HEDLEY_STATIC_CAST(__mmask32, ~UINT32_C(0)));
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#else
|
||||
simde_svint8_t r;
|
||||
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntb()) ; i++) {
|
||||
r.values[i] = ~INT8_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint8(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svptrue_b8
|
||||
#define svptrue_b8() simde_svptrue_b8()
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svptrue_b16(void) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svptrue_b16();
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
simde_svbool_t r;
|
||||
|
||||
#if SIMDE_ARM_SVE_VECTOR_SIZE >= 512
|
||||
r = simde_svbool_from_mmask32(HEDLEY_STATIC_CAST(__mmask32, ~UINT32_C(0)));
|
||||
#else
|
||||
r = simde_svbool_from_mmask16(HEDLEY_STATIC_CAST(__mmask16, ~UINT16_C(0)));
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#else
|
||||
simde_svint16_t r;
|
||||
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcnth()) ; i++) {
|
||||
r.values[i] = ~INT16_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint16(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svptrue_b16
|
||||
#define svptrue_b16() simde_svptrue_b16()
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svptrue_b32(void) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svptrue_b32();
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
simde_svbool_t r;
|
||||
|
||||
#if SIMDE_ARM_SVE_VECTOR_SIZE >= 512
|
||||
r = simde_svbool_from_mmask32(HEDLEY_STATIC_CAST(__mmask16, ~UINT16_C(0)));
|
||||
#else
|
||||
r = simde_svbool_from_mmask8(HEDLEY_STATIC_CAST(__mmask8, ~UINT8_C(0)));
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#else
|
||||
simde_svint32_t r;
|
||||
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntw()) ; i++) {
|
||||
r.values[i] = ~INT32_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint32(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svptrue_b32
|
||||
#define svptrue_b32() simde_svptrue_b32()
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svptrue_b64(void) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svptrue_b64();
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
simde_svbool_t r;
|
||||
|
||||
#if SIMDE_ARM_SVE_VECTOR_SIZE >= 512
|
||||
r = simde_svbool_from_mmask8(HEDLEY_STATIC_CAST(__mmask8, ~UINT8_C(0)));
|
||||
#else
|
||||
r = simde_svbool_from_mmask4(HEDLEY_STATIC_CAST(__mmask8, ~UINT8_C(0)));
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#else
|
||||
simde_svint64_t r;
|
||||
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntd()) ; i++) {
|
||||
r.values[i] = ~INT64_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint64(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svptrue_b64
|
||||
#define svptrue_b64() simde_svptrue_b64()
|
||||
#endif
|
||||
|
||||
HEDLEY_DIAGNOSTIC_POP
|
||||
|
||||
#endif /* SIMDE_ARM_SVE_PTRUE_H */
|
||||
@@ -0,0 +1,498 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use, copy,
|
||||
* modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
* of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Copyright:
|
||||
* 2021 Evan Nemerson <evan@nemerson.com>
|
||||
*/
|
||||
|
||||
#if !defined(SIMDE_ARM_SVE_QADD_H)
|
||||
#define SIMDE_ARM_SVE_QADD_H
|
||||
|
||||
#include "types.h"
|
||||
#include "sel.h"
|
||||
#include "dup.h"
|
||||
|
||||
HEDLEY_DIAGNOSTIC_PUSH
|
||||
SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint8_t
|
||||
simde_svqadd_s8(simde_svint8_t op1, simde_svint8_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_s8(op1, op2);
|
||||
#else
|
||||
simde_svint8_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vqaddq_s8(op1.neon, op2.neon);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
r.m512i = _mm512_adds_epi8(op1.m512i, op2.m512i);
|
||||
#elif defined(SIMDE_X86_AVX2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m256i) / sizeof(r.m256i[0])) ; i++) {
|
||||
r.m256i[i] = _mm256_adds_epi8(op1.m256i[i], op2.m256i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_adds_epi8(op1.m128i[i], op2.m128i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
|
||||
r.altivec = vec_adds(op1.altivec, op2.altivec);
|
||||
#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec =
|
||||
vec_packs(
|
||||
vec_unpackh(op1.altivec) + vec_unpackh(op2.altivec),
|
||||
vec_unpackl(op1.altivec) + vec_unpackl(op2.altivec)
|
||||
);
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_i8x16_add_sat(op1.v128, op2.v128);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = simde_math_adds_i8(op1.values[i], op2.values[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_s8
|
||||
#define svqadd_s8(op1, op2) simde_svqadd_s8(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint8_t
|
||||
simde_svqadd_n_s8(simde_svint8_t op1, int8_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_n_s8(op1, op2);
|
||||
#else
|
||||
return simde_svqadd_s8(op1, simde_svdup_n_s8(op2));
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_n_s8
|
||||
#define svqadd_n_s8(op1, op2) simde_svqadd_n_s8(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint16_t
|
||||
simde_svqadd_s16(simde_svint16_t op1, simde_svint16_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_s16(op1, op2);
|
||||
#else
|
||||
simde_svint16_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vqaddq_s16(op1.neon, op2.neon);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
r.m512i = _mm512_adds_epi16(op1.m512i, op2.m512i);
|
||||
#elif defined(SIMDE_X86_AVX2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m256i) / sizeof(r.m256i[0])) ; i++) {
|
||||
r.m256i[i] = _mm256_adds_epi16(op1.m256i[i], op2.m256i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_adds_epi16(op1.m128i[i], op2.m128i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
|
||||
r.altivec = vec_adds(op1.altivec, op2.altivec);
|
||||
#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec =
|
||||
vec_packs(
|
||||
vec_unpackh(op1.altivec) + vec_unpackh(op2.altivec),
|
||||
vec_unpackl(op1.altivec) + vec_unpackl(op2.altivec)
|
||||
);
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_i16x8_add_sat(op1.v128, op2.v128);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = simde_math_adds_i16(op1.values[i], op2.values[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_s16
|
||||
#define svqadd_s16(op1, op2) simde_svqadd_s16(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint16_t
|
||||
simde_svqadd_n_s16(simde_svint16_t op1, int16_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_n_s16(op1, op2);
|
||||
#else
|
||||
return simde_svqadd_s16(op1, simde_svdup_n_s16(op2));
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_n_s16
|
||||
#define svqadd_n_s16(op1, op2) simde_svqadd_n_s16(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint32_t
|
||||
simde_svqadd_s32(simde_svint32_t op1, simde_svint32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_s32(op1, op2);
|
||||
#else
|
||||
simde_svint32_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vqaddq_s32(op1.neon, op2.neon);
|
||||
#elif defined(SIMDE_X86_AVX512VL_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m256i) / sizeof(r.m256i[0])) ; i++) {
|
||||
r.m256i[i] = _mm512_cvtsepi64_epi32(_mm512_add_epi64(_mm512_cvtepi32_epi64(op1.m256i[i]), _mm512_cvtepi32_epi64(op2.m256i[i])));
|
||||
}
|
||||
#elif defined(SIMDE_X86_AVX512VL_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm256_cvtsepi64_epi32(_mm256_add_epi64(_mm256_cvtepi32_epi64(op1.m128i[i]), _mm256_cvtepi32_epi64(op2.m128i[i])));
|
||||
}
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
|
||||
r.altivec = vec_adds(op1.altivec, op2.altivec);
|
||||
#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec =
|
||||
vec_packs(
|
||||
vec_unpackh(op1.altivec) + vec_unpackh(op2.altivec),
|
||||
vec_unpackl(op1.altivec) + vec_unpackl(op2.altivec)
|
||||
);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = simde_math_adds_i32(op1.values[i], op2.values[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_s32
|
||||
#define svqadd_s32(op1, op2) simde_svqadd_s32(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint32_t
|
||||
simde_svqadd_n_s32(simde_svint32_t op1, int32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_n_s32(op1, op2);
|
||||
#else
|
||||
return simde_svqadd_s32(op1, simde_svdup_n_s32(op2));
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_n_s32
|
||||
#define svqadd_n_s32(op1, op2) simde_svqadd_n_s32(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint64_t
|
||||
simde_svqadd_s64(simde_svint64_t op1, simde_svint64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_s64(op1, op2);
|
||||
#else
|
||||
simde_svint64_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vqaddq_s64(op1.neon, op2.neon);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = simde_math_adds_i64(op1.values[i], op2.values[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_s64
|
||||
#define svqadd_s64(op1, op2) simde_svqadd_s64(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint64_t
|
||||
simde_svqadd_n_s64(simde_svint64_t op1, int64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_n_s64(op1, op2);
|
||||
#else
|
||||
return simde_svqadd_s64(op1, simde_svdup_n_s64(op2));
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_n_s64
|
||||
#define svqadd_n_s64(op1, op2) simde_svqadd_n_s64(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint8_t
|
||||
simde_svqadd_u8(simde_svuint8_t op1, simde_svuint8_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_u8(op1, op2);
|
||||
#else
|
||||
simde_svuint8_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vqaddq_u8(op1.neon, op2.neon);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
r.m512i = _mm512_adds_epu8(op1.m512i, op2.m512i);
|
||||
#elif defined(SIMDE_X86_AVX2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m256i) / sizeof(r.m256i[0])) ; i++) {
|
||||
r.m256i[i] = _mm256_adds_epu8(op1.m256i[i], op2.m256i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_adds_epu8(op1.m128i[i], op2.m128i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
|
||||
r.altivec = vec_adds(op1.altivec, op2.altivec);
|
||||
#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec =
|
||||
vec_packs(
|
||||
vec_unpackh(op1.altivec) + vec_unpackh(op2.altivec),
|
||||
vec_unpackl(op1.altivec) + vec_unpackl(op2.altivec)
|
||||
);
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_u8x16_add_sat(op1.v128, op2.v128);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = simde_math_adds_u8(op1.values[i], op2.values[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_u8
|
||||
#define svqadd_u8(op1, op2) simde_svqadd_u8(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint8_t
|
||||
simde_svqadd_n_u8(simde_svuint8_t op1, uint8_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_n_u8(op1, op2);
|
||||
#else
|
||||
return simde_svqadd_u8(op1, simde_svdup_n_u8(op2));
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_n_u8
|
||||
#define svqadd_n_u8(op1, op2) simde_svqadd_n_u8(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint16_t
|
||||
simde_svqadd_u16(simde_svuint16_t op1, simde_svuint16_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_u16(op1, op2);
|
||||
#else
|
||||
simde_svuint16_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vqaddq_u16(op1.neon, op2.neon);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
r.m512i = _mm512_adds_epu16(op1.m512i, op2.m512i);
|
||||
#elif defined(SIMDE_X86_AVX2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m256i) / sizeof(r.m256i[0])) ; i++) {
|
||||
r.m256i[i] = _mm256_adds_epu16(op1.m256i[i], op2.m256i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_adds_epu16(op1.m128i[i], op2.m128i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
|
||||
r.altivec = vec_adds(op1.altivec, op2.altivec);
|
||||
#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec =
|
||||
vec_packs(
|
||||
vec_unpackh(op1.altivec) + vec_unpackh(op2.altivec),
|
||||
vec_unpackl(op1.altivec) + vec_unpackl(op2.altivec)
|
||||
);
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_u16x8_add_sat(op1.v128, op2.v128);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = simde_math_adds_u16(op1.values[i], op2.values[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_u16
|
||||
#define svqadd_u16(op1, op2) simde_svqadd_u16(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint16_t
|
||||
simde_svqadd_n_u16(simde_svuint16_t op1, uint16_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_n_u16(op1, op2);
|
||||
#else
|
||||
return simde_svqadd_u16(op1, simde_svdup_n_u16(op2));
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_n_u16
|
||||
#define svqadd_n_u16(op1, op2) simde_svqadd_n_u16(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint32_t
|
||||
simde_svqadd_u32(simde_svuint32_t op1, simde_svuint32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_u32(op1, op2);
|
||||
#else
|
||||
simde_svuint32_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vqaddq_u32(op1.neon, op2.neon);
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
|
||||
r.altivec = vec_adds(op1.altivec, op2.altivec);
|
||||
#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec =
|
||||
vec_packs(
|
||||
vec_unpackh(op1.altivec) + vec_unpackh(op2.altivec),
|
||||
vec_unpackl(op1.altivec) + vec_unpackl(op2.altivec)
|
||||
);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = simde_math_adds_u32(op1.values[i], op2.values[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_u32
|
||||
#define svqadd_u32(op1, op2) simde_svqadd_u32(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint32_t
|
||||
simde_svqadd_n_u32(simde_svuint32_t op1, uint32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_n_u32(op1, op2);
|
||||
#else
|
||||
return simde_svqadd_u32(op1, simde_svdup_n_u32(op2));
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_n_u32
|
||||
#define svqadd_n_u32(op1, op2) simde_svqadd_n_u32(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint64_t
|
||||
simde_svqadd_u64(simde_svuint64_t op1, simde_svuint64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_u64(op1, op2);
|
||||
#else
|
||||
simde_svuint64_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vqaddq_u64(op1.neon, op2.neon);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = simde_math_adds_u64(op1.values[i], op2.values[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_u64
|
||||
#define svqadd_u64(op1, op2) simde_svqadd_u64(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint64_t
|
||||
simde_svqadd_n_u64(simde_svuint64_t op1, uint64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svqadd_n_u64(op1, op2);
|
||||
#else
|
||||
return simde_svqadd_u64(op1, simde_svdup_n_u64(op2));
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svqadd_n_u64
|
||||
#define svqadd_n_u64(op1, op2) simde_svqadd_n_u64(op1, op2)
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svqadd( simde_svint8_t op1, simde_svint8_t op2) { return simde_svqadd_s8 (op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svqadd( simde_svint16_t op1, simde_svint16_t op2) { return simde_svqadd_s16 (op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svqadd( simde_svint32_t op1, simde_svint32_t op2) { return simde_svqadd_s32 (op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svqadd( simde_svint64_t op1, simde_svint64_t op2) { return simde_svqadd_s64 (op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svqadd( simde_svuint8_t op1, simde_svuint8_t op2) { return simde_svqadd_u8 (op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svqadd( simde_svuint16_t op1, simde_svuint16_t op2) { return simde_svqadd_u16 (op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svqadd( simde_svuint32_t op1, simde_svuint32_t op2) { return simde_svqadd_u32 (op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svqadd( simde_svuint64_t op1, simde_svuint64_t op2) { return simde_svqadd_u64 (op1, op2); }
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svqadd( simde_svint8_t op1, int8_t op2) { return simde_svqadd_n_s8 (op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svqadd( simde_svint16_t op1, int16_t op2) { return simde_svqadd_n_s16(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svqadd( simde_svint32_t op1, int32_t op2) { return simde_svqadd_n_s32(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svqadd( simde_svint64_t op1, int64_t op2) { return simde_svqadd_n_s64(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svqadd( simde_svuint8_t op1, uint8_t op2) { return simde_svqadd_n_u8 (op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svqadd( simde_svuint16_t op1, uint16_t op2) { return simde_svqadd_n_u16(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svqadd( simde_svuint32_t op1, uint32_t op2) { return simde_svqadd_n_u32(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svqadd( simde_svuint64_t op1, uint64_t op2) { return simde_svqadd_n_u64(op1, op2); }
|
||||
#elif defined(SIMDE_GENERIC_)
|
||||
#define simde_svqadd_x(op1, op2) \
|
||||
(SIMDE_GENERIC_((op2), \
|
||||
simde_svint8_t: simde_svqadd_s8, \
|
||||
simde_svint16_t: simde_svqadd_s16, \
|
||||
simde_svint32_t: simde_svqadd_s32, \
|
||||
simde_svint64_t: simde_svqadd_s64, \
|
||||
simde_svuint8_t: simde_svqadd_u8, \
|
||||
simde_svuint16_t: simde_svqadd_u16, \
|
||||
simde_svuint32_t: simde_svqadd_u32, \
|
||||
simde_svuint64_t: simde_svqadd_u64, \
|
||||
int8_t: simde_svqadd_n_s8, \
|
||||
int16_t: simde_svqadd_n_s16, \
|
||||
int32_t: simde_svqadd_n_s32, \
|
||||
int64_t: simde_svqadd_n_s64, \
|
||||
uint8_t: simde_svqadd_n_u8, \
|
||||
uint16_t: simde_svqadd_n_u16, \
|
||||
uint32_t: simde_svqadd_n_u32, \
|
||||
uint64_t: simde_svqadd_n_u64)((pg), (op1), (op2)))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef svqadd
|
||||
#define svqadd(op1, op2) simde_svqadd((pg), (op1), (op2))
|
||||
#endif
|
||||
|
||||
HEDLEY_DIAGNOSTIC_POP
|
||||
|
||||
#endif /* SIMDE_ARM_SVE_QADD_H */
|
||||
@@ -0,0 +1,754 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use, copy,
|
||||
* modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
* of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Copyright:
|
||||
* 2021 Evan Nemerson <evan@nemerson.com>
|
||||
*/
|
||||
|
||||
#if !defined(SIMDE_ARM_SVE_REINTERPRET_H)
|
||||
#define SIMDE_ARM_SVE_REINTERPRET_H
|
||||
|
||||
#include "types.h"
|
||||
|
||||
HEDLEY_DIAGNOSTIC_PUSH
|
||||
SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
|
||||
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8_s16( simde_svint16_t op) { return svreinterpret_s8_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8_s32( simde_svint32_t op) { return svreinterpret_s8_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8_s64( simde_svint64_t op) { return svreinterpret_s8_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8_u8( simde_svuint8_t op) { return svreinterpret_s8_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8_u16( simde_svuint16_t op) { return svreinterpret_s8_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8_u32( simde_svuint32_t op) { return svreinterpret_s8_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8_u64( simde_svuint64_t op) { return svreinterpret_s8_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8_f16( simde_svfloat16_t op) { return svreinterpret_s8_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8_f32( simde_svfloat32_t op) { return svreinterpret_s8_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8_f64( simde_svfloat64_t op) { return svreinterpret_s8_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16_s8( simde_svint8_t op) { return svreinterpret_s16_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16_s32( simde_svint32_t op) { return svreinterpret_s16_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16_s64( simde_svint64_t op) { return svreinterpret_s16_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16_u8( simde_svuint8_t op) { return svreinterpret_s16_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16_u16( simde_svuint16_t op) { return svreinterpret_s16_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16_u32( simde_svuint32_t op) { return svreinterpret_s16_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16_u64( simde_svuint64_t op) { return svreinterpret_s16_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16_f16( simde_svfloat16_t op) { return svreinterpret_s16_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16_f32( simde_svfloat32_t op) { return svreinterpret_s16_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16_f64( simde_svfloat64_t op) { return svreinterpret_s16_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32_s8( simde_svint8_t op) { return svreinterpret_s32_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32_s16( simde_svint16_t op) { return svreinterpret_s32_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32_s64( simde_svint64_t op) { return svreinterpret_s32_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32_u8( simde_svuint8_t op) { return svreinterpret_s32_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32_u16( simde_svuint16_t op) { return svreinterpret_s32_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32_u32( simde_svuint32_t op) { return svreinterpret_s32_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32_u64( simde_svuint64_t op) { return svreinterpret_s32_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32_f16( simde_svfloat16_t op) { return svreinterpret_s32_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32_f32( simde_svfloat32_t op) { return svreinterpret_s32_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32_f64( simde_svfloat64_t op) { return svreinterpret_s32_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64_s8( simde_svint8_t op) { return svreinterpret_s64_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64_s16( simde_svint16_t op) { return svreinterpret_s64_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64_s32( simde_svint32_t op) { return svreinterpret_s64_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64_u8( simde_svuint8_t op) { return svreinterpret_s64_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64_u16( simde_svuint16_t op) { return svreinterpret_s64_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64_u32( simde_svuint32_t op) { return svreinterpret_s64_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64_u64( simde_svuint64_t op) { return svreinterpret_s64_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64_f16( simde_svfloat16_t op) { return svreinterpret_s64_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64_f32( simde_svfloat32_t op) { return svreinterpret_s64_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64_f64( simde_svfloat64_t op) { return svreinterpret_s64_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8_s8( simde_svint8_t op) { return svreinterpret_u8_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8_s16( simde_svint16_t op) { return svreinterpret_u8_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8_s32( simde_svint32_t op) { return svreinterpret_u8_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8_s64( simde_svint64_t op) { return svreinterpret_u8_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8_u16( simde_svuint16_t op) { return svreinterpret_u8_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8_u32( simde_svuint32_t op) { return svreinterpret_u8_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8_u64( simde_svuint64_t op) { return svreinterpret_u8_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8_f16( simde_svfloat16_t op) { return svreinterpret_u8_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8_f32( simde_svfloat32_t op) { return svreinterpret_u8_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8_f64( simde_svfloat64_t op) { return svreinterpret_u8_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16_s8( simde_svint8_t op) { return svreinterpret_u16_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16_s16( simde_svint16_t op) { return svreinterpret_u16_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16_s32( simde_svint32_t op) { return svreinterpret_u16_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16_s64( simde_svint64_t op) { return svreinterpret_u16_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16_u8( simde_svuint8_t op) { return svreinterpret_u16_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16_u32( simde_svuint32_t op) { return svreinterpret_u16_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16_u64( simde_svuint64_t op) { return svreinterpret_u16_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16_f16( simde_svfloat16_t op) { return svreinterpret_u16_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16_f32( simde_svfloat32_t op) { return svreinterpret_u16_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16_f64( simde_svfloat64_t op) { return svreinterpret_u16_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32_s8( simde_svint8_t op) { return svreinterpret_u32_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32_s16( simde_svint16_t op) { return svreinterpret_u32_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32_s32( simde_svint32_t op) { return svreinterpret_u32_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32_s64( simde_svint64_t op) { return svreinterpret_u32_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32_u8( simde_svuint8_t op) { return svreinterpret_u32_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32_u16( simde_svuint16_t op) { return svreinterpret_u32_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32_u64( simde_svuint64_t op) { return svreinterpret_u32_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32_f16( simde_svfloat16_t op) { return svreinterpret_u32_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32_f32( simde_svfloat32_t op) { return svreinterpret_u32_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32_f64( simde_svfloat64_t op) { return svreinterpret_u32_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64_s8( simde_svint8_t op) { return svreinterpret_u64_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64_s16( simde_svint16_t op) { return svreinterpret_u64_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64_s32( simde_svint32_t op) { return svreinterpret_u64_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64_s64( simde_svint64_t op) { return svreinterpret_u64_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64_u8( simde_svuint8_t op) { return svreinterpret_u64_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64_u16( simde_svuint16_t op) { return svreinterpret_u64_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64_u32( simde_svuint32_t op) { return svreinterpret_u64_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64_f16( simde_svfloat16_t op) { return svreinterpret_u64_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64_f32( simde_svfloat32_t op) { return svreinterpret_u64_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64_f64( simde_svfloat64_t op) { return svreinterpret_u64_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16_s8( simde_svint8_t op) { return svreinterpret_f16_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16_s16( simde_svint16_t op) { return svreinterpret_f16_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16_s32( simde_svint32_t op) { return svreinterpret_f16_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16_s64( simde_svint64_t op) { return svreinterpret_f16_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16_u8( simde_svuint8_t op) { return svreinterpret_f16_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16_u16( simde_svuint16_t op) { return svreinterpret_f16_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16_u32( simde_svuint32_t op) { return svreinterpret_f16_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16_u64( simde_svuint64_t op) { return svreinterpret_f16_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16_f32( simde_svfloat32_t op) { return svreinterpret_f16_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16_f64( simde_svfloat64_t op) { return svreinterpret_f16_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32_s8( simde_svint8_t op) { return svreinterpret_f32_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32_s16( simde_svint16_t op) { return svreinterpret_f32_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32_s32( simde_svint32_t op) { return svreinterpret_f32_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32_s64( simde_svint64_t op) { return svreinterpret_f32_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32_u8( simde_svuint8_t op) { return svreinterpret_f32_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32_u16( simde_svuint16_t op) { return svreinterpret_f32_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32_u32( simde_svuint32_t op) { return svreinterpret_f32_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32_u64( simde_svuint64_t op) { return svreinterpret_f32_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32_f16( simde_svfloat16_t op) { return svreinterpret_f32_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32_f64( simde_svfloat64_t op) { return svreinterpret_f32_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64_s8( simde_svint8_t op) { return svreinterpret_f64_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64_s16( simde_svint16_t op) { return svreinterpret_f64_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64_s32( simde_svint32_t op) { return svreinterpret_f64_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64_s64( simde_svint64_t op) { return svreinterpret_f64_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64_u8( simde_svuint8_t op) { return svreinterpret_f64_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64_u16( simde_svuint16_t op) { return svreinterpret_f64_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64_u32( simde_svuint32_t op) { return svreinterpret_f64_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64_u64( simde_svuint64_t op) { return svreinterpret_f64_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64_f16( simde_svfloat16_t op) { return svreinterpret_f64_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64_f32( simde_svfloat32_t op) { return svreinterpret_f64_f32(op); }
|
||||
#else
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s8_s16, simde_svint8_t, simde_svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s8_s32, simde_svint8_t, simde_svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s8_s64, simde_svint8_t, simde_svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s8_u8, simde_svint8_t, simde_svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s8_u16, simde_svint8_t, simde_svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s8_u32, simde_svint8_t, simde_svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s8_u64, simde_svint8_t, simde_svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s8_f16, simde_svint8_t, simde_svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s8_f32, simde_svint8_t, simde_svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s8_f64, simde_svint8_t, simde_svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s16_s8, simde_svint16_t, simde_svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s16_s32, simde_svint16_t, simde_svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s16_s64, simde_svint16_t, simde_svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s16_u8, simde_svint16_t, simde_svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s16_u16, simde_svint16_t, simde_svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s16_u32, simde_svint16_t, simde_svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s16_u64, simde_svint16_t, simde_svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s16_f16, simde_svint16_t, simde_svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s16_f32, simde_svint16_t, simde_svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s16_f64, simde_svint16_t, simde_svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s32_s8, simde_svint32_t, simde_svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s32_s16, simde_svint32_t, simde_svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s32_s64, simde_svint32_t, simde_svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s32_u8, simde_svint32_t, simde_svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s32_u16, simde_svint32_t, simde_svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s32_u32, simde_svint32_t, simde_svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s32_u64, simde_svint32_t, simde_svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s32_f16, simde_svint32_t, simde_svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s32_f32, simde_svint32_t, simde_svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s32_f64, simde_svint32_t, simde_svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s64_s8, simde_svint64_t, simde_svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s64_s16, simde_svint64_t, simde_svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s64_s32, simde_svint64_t, simde_svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s64_u8, simde_svint64_t, simde_svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s64_u16, simde_svint64_t, simde_svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s64_u32, simde_svint64_t, simde_svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s64_u64, simde_svint64_t, simde_svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s64_f16, simde_svint64_t, simde_svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s64_f32, simde_svint64_t, simde_svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_s64_f64, simde_svint64_t, simde_svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u8_s8, simde_svuint8_t, simde_svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u8_s16, simde_svuint8_t, simde_svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u8_s32, simde_svuint8_t, simde_svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u8_s64, simde_svuint8_t, simde_svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u8_u16, simde_svuint8_t, simde_svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u8_u32, simde_svuint8_t, simde_svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u8_u64, simde_svuint8_t, simde_svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u8_f16, simde_svuint8_t, simde_svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u8_f32, simde_svuint8_t, simde_svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u8_f64, simde_svuint8_t, simde_svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u16_s8, simde_svuint16_t, simde_svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u16_s16, simde_svuint16_t, simde_svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u16_s32, simde_svuint16_t, simde_svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u16_s64, simde_svuint16_t, simde_svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u16_u8, simde_svuint16_t, simde_svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u16_u32, simde_svuint16_t, simde_svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u16_u64, simde_svuint16_t, simde_svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u16_f16, simde_svuint16_t, simde_svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u16_f32, simde_svuint16_t, simde_svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u16_f64, simde_svuint16_t, simde_svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u32_s8, simde_svuint32_t, simde_svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u32_s16, simde_svuint32_t, simde_svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u32_s32, simde_svuint32_t, simde_svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u32_s64, simde_svuint32_t, simde_svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u32_u8, simde_svuint32_t, simde_svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u32_u16, simde_svuint32_t, simde_svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u32_u64, simde_svuint32_t, simde_svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u32_f16, simde_svuint32_t, simde_svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u32_f32, simde_svuint32_t, simde_svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u32_f64, simde_svuint32_t, simde_svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u64_s8, simde_svuint64_t, simde_svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u64_s16, simde_svuint64_t, simde_svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u64_s32, simde_svuint64_t, simde_svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u64_s64, simde_svuint64_t, simde_svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u64_u8, simde_svuint64_t, simde_svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u64_u16, simde_svuint64_t, simde_svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u64_u32, simde_svuint64_t, simde_svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u64_f16, simde_svuint64_t, simde_svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u64_f32, simde_svuint64_t, simde_svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_u64_f64, simde_svuint64_t, simde_svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f16_s8, simde_svfloat16_t, simde_svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f16_s16, simde_svfloat16_t, simde_svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f16_s32, simde_svfloat16_t, simde_svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f16_s64, simde_svfloat16_t, simde_svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f16_u8, simde_svfloat16_t, simde_svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f16_u16, simde_svfloat16_t, simde_svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f16_u32, simde_svfloat16_t, simde_svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f16_u64, simde_svfloat16_t, simde_svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f16_f32, simde_svfloat16_t, simde_svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f16_f64, simde_svfloat16_t, simde_svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f32_s8, simde_svfloat32_t, simde_svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f32_s16, simde_svfloat32_t, simde_svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f32_s32, simde_svfloat32_t, simde_svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f32_s64, simde_svfloat32_t, simde_svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f32_u8, simde_svfloat32_t, simde_svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f32_u16, simde_svfloat32_t, simde_svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f32_u32, simde_svfloat32_t, simde_svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f32_u64, simde_svfloat32_t, simde_svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f32_f16, simde_svfloat32_t, simde_svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f32_f64, simde_svfloat32_t, simde_svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f64_s8, simde_svfloat64_t, simde_svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f64_s16, simde_svfloat64_t, simde_svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f64_s32, simde_svfloat64_t, simde_svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f64_s64, simde_svfloat64_t, simde_svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f64_u8, simde_svfloat64_t, simde_svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f64_u16, simde_svfloat64_t, simde_svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f64_u32, simde_svfloat64_t, simde_svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f64_u64, simde_svfloat64_t, simde_svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f64_f16, simde_svfloat64_t, simde_svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svreinterpret_f64_f32, simde_svfloat64_t, simde_svfloat32_t)
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8( simde_svint16_t op) { return simde_svreinterpret_s8_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8( simde_svint32_t op) { return simde_svreinterpret_s8_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8( simde_svint64_t op) { return simde_svreinterpret_s8_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8( simde_svuint8_t op) { return simde_svreinterpret_s8_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8( simde_svuint16_t op) { return simde_svreinterpret_s8_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8( simde_svuint32_t op) { return simde_svreinterpret_s8_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8( simde_svuint64_t op) { return simde_svreinterpret_s8_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8( simde_svfloat16_t op) { return simde_svreinterpret_s8_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8( simde_svfloat32_t op) { return simde_svreinterpret_s8_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svreinterpret_s8( simde_svfloat64_t op) { return simde_svreinterpret_s8_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16( simde_svint8_t op) { return simde_svreinterpret_s16_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16( simde_svint32_t op) { return simde_svreinterpret_s16_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16( simde_svint64_t op) { return simde_svreinterpret_s16_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16( simde_svuint8_t op) { return simde_svreinterpret_s16_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16( simde_svuint16_t op) { return simde_svreinterpret_s16_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16( simde_svuint32_t op) { return simde_svreinterpret_s16_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16( simde_svuint64_t op) { return simde_svreinterpret_s16_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16( simde_svfloat16_t op) { return simde_svreinterpret_s16_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16( simde_svfloat32_t op) { return simde_svreinterpret_s16_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svreinterpret_s16( simde_svfloat64_t op) { return simde_svreinterpret_s16_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32( simde_svint8_t op) { return simde_svreinterpret_s32_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32( simde_svint16_t op) { return simde_svreinterpret_s32_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32( simde_svint64_t op) { return simde_svreinterpret_s32_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32( simde_svuint8_t op) { return simde_svreinterpret_s32_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32( simde_svuint16_t op) { return simde_svreinterpret_s32_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32( simde_svuint32_t op) { return simde_svreinterpret_s32_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32( simde_svuint64_t op) { return simde_svreinterpret_s32_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32( simde_svfloat16_t op) { return simde_svreinterpret_s32_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32( simde_svfloat32_t op) { return simde_svreinterpret_s32_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svreinterpret_s32( simde_svfloat64_t op) { return simde_svreinterpret_s32_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64( simde_svint8_t op) { return simde_svreinterpret_s64_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64( simde_svint16_t op) { return simde_svreinterpret_s64_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64( simde_svint32_t op) { return simde_svreinterpret_s64_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64( simde_svuint8_t op) { return simde_svreinterpret_s64_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64( simde_svuint16_t op) { return simde_svreinterpret_s64_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64( simde_svuint32_t op) { return simde_svreinterpret_s64_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64( simde_svuint64_t op) { return simde_svreinterpret_s64_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64( simde_svfloat16_t op) { return simde_svreinterpret_s64_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64( simde_svfloat32_t op) { return simde_svreinterpret_s64_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svreinterpret_s64( simde_svfloat64_t op) { return simde_svreinterpret_s64_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8( simde_svint8_t op) { return simde_svreinterpret_u8_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8( simde_svint16_t op) { return simde_svreinterpret_u8_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8( simde_svint32_t op) { return simde_svreinterpret_u8_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8( simde_svint64_t op) { return simde_svreinterpret_u8_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8( simde_svuint16_t op) { return simde_svreinterpret_u8_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8( simde_svuint32_t op) { return simde_svreinterpret_u8_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8( simde_svuint64_t op) { return simde_svreinterpret_u8_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8( simde_svfloat16_t op) { return simde_svreinterpret_u8_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8( simde_svfloat32_t op) { return simde_svreinterpret_u8_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svreinterpret_u8( simde_svfloat64_t op) { return simde_svreinterpret_u8_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16( simde_svint8_t op) { return simde_svreinterpret_u16_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16( simde_svint16_t op) { return simde_svreinterpret_u16_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16( simde_svint32_t op) { return simde_svreinterpret_u16_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16( simde_svint64_t op) { return simde_svreinterpret_u16_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16( simde_svuint8_t op) { return simde_svreinterpret_u16_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16( simde_svuint32_t op) { return simde_svreinterpret_u16_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16( simde_svuint64_t op) { return simde_svreinterpret_u16_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16( simde_svfloat16_t op) { return simde_svreinterpret_u16_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16( simde_svfloat32_t op) { return simde_svreinterpret_u16_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svreinterpret_u16( simde_svfloat64_t op) { return simde_svreinterpret_u16_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32( simde_svint8_t op) { return simde_svreinterpret_u32_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32( simde_svint16_t op) { return simde_svreinterpret_u32_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32( simde_svint32_t op) { return simde_svreinterpret_u32_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32( simde_svint64_t op) { return simde_svreinterpret_u32_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32( simde_svuint8_t op) { return simde_svreinterpret_u32_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32( simde_svuint16_t op) { return simde_svreinterpret_u32_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32( simde_svuint64_t op) { return simde_svreinterpret_u32_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32( simde_svfloat16_t op) { return simde_svreinterpret_u32_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32( simde_svfloat32_t op) { return simde_svreinterpret_u32_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svreinterpret_u32( simde_svfloat64_t op) { return simde_svreinterpret_u32_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64( simde_svint8_t op) { return simde_svreinterpret_u64_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64( simde_svint16_t op) { return simde_svreinterpret_u64_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64( simde_svint32_t op) { return simde_svreinterpret_u64_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64( simde_svint64_t op) { return simde_svreinterpret_u64_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64( simde_svuint8_t op) { return simde_svreinterpret_u64_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64( simde_svuint16_t op) { return simde_svreinterpret_u64_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64( simde_svuint32_t op) { return simde_svreinterpret_u64_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64( simde_svfloat16_t op) { return simde_svreinterpret_u64_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64( simde_svfloat32_t op) { return simde_svreinterpret_u64_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svreinterpret_u64( simde_svfloat64_t op) { return simde_svreinterpret_u64_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16( simde_svint8_t op) { return simde_svreinterpret_f16_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16( simde_svint16_t op) { return simde_svreinterpret_f16_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16( simde_svint32_t op) { return simde_svreinterpret_f16_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16( simde_svint64_t op) { return simde_svreinterpret_f16_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16( simde_svuint8_t op) { return simde_svreinterpret_f16_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16( simde_svuint16_t op) { return simde_svreinterpret_f16_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16( simde_svuint32_t op) { return simde_svreinterpret_f16_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16( simde_svuint64_t op) { return simde_svreinterpret_f16_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16( simde_svfloat32_t op) { return simde_svreinterpret_f16_f32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat16_t simde_svreinterpret_f16( simde_svfloat64_t op) { return simde_svreinterpret_f16_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32( simde_svint8_t op) { return simde_svreinterpret_f32_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32( simde_svint16_t op) { return simde_svreinterpret_f32_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32( simde_svint32_t op) { return simde_svreinterpret_f32_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32( simde_svint64_t op) { return simde_svreinterpret_f32_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32( simde_svuint8_t op) { return simde_svreinterpret_f32_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32( simde_svuint16_t op) { return simde_svreinterpret_f32_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32( simde_svuint32_t op) { return simde_svreinterpret_f32_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32( simde_svuint64_t op) { return simde_svreinterpret_f32_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32( simde_svfloat16_t op) { return simde_svreinterpret_f32_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svreinterpret_f32( simde_svfloat64_t op) { return simde_svreinterpret_f32_f64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64( simde_svint8_t op) { return simde_svreinterpret_f64_s8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64( simde_svint16_t op) { return simde_svreinterpret_f64_s16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64( simde_svint32_t op) { return simde_svreinterpret_f64_s32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64( simde_svint64_t op) { return simde_svreinterpret_f64_s64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64( simde_svuint8_t op) { return simde_svreinterpret_f64_u8(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64( simde_svuint16_t op) { return simde_svreinterpret_f64_u16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64( simde_svuint32_t op) { return simde_svreinterpret_f64_u32(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64( simde_svuint64_t op) { return simde_svreinterpret_f64_u64(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64( simde_svfloat16_t op) { return simde_svreinterpret_f64_f16(op); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svreinterpret_f64( simde_svfloat32_t op) { return simde_svreinterpret_f64_f32(op); }
|
||||
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s8, svint8_t, svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s8, svint8_t, svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s8, svint8_t, svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s8, svint8_t, svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s8, svint8_t, svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s8, svint8_t, svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s8, svint8_t, svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s8, svint8_t, svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s8, svint8_t, svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s8, svint8_t, svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s16, svint16_t, svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s16, svint16_t, svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s16, svint16_t, svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s16, svint16_t, svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s16, svint16_t, svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s16, svint16_t, svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s16, svint16_t, svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s16, svint16_t, svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s16, svint16_t, svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s16, svint16_t, svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s32, svint32_t, svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s32, svint32_t, svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s32, svint32_t, svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s32, svint32_t, svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s32, svint32_t, svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s32, svint32_t, svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s32, svint32_t, svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s32, svint32_t, svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s32, svint32_t, svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s32, svint32_t, svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s64, svint64_t, svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s64, svint64_t, svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s64, svint64_t, svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s64, svint64_t, svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s64, svint64_t, svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s64, svint64_t, svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s64, svint64_t, svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s64, svint64_t, svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s64, svint64_t, svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_s64, svint64_t, svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u8, svuint8_t, svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u8, svuint8_t, svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u8, svuint8_t, svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u8, svuint8_t, svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u8, svuint8_t, svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u8, svuint8_t, svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u8, svuint8_t, svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u8, svuint8_t, svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u8, svuint8_t, svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u8, svuint8_t, svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u16, svuint16_t, svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u16, svuint16_t, svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u16, svuint16_t, svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u16, svuint16_t, svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u16, svuint16_t, svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u16, svuint16_t, svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u16, svuint16_t, svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u16, svuint16_t, svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u16, svuint16_t, svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u16, svuint16_t, svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u32, svuint32_t, svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u32, svuint32_t, svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u32, svuint32_t, svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u32, svuint32_t, svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u32, svuint32_t, svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u32, svuint32_t, svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u32, svuint32_t, svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u32, svuint32_t, svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u32, svuint32_t, svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u32, svuint32_t, svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u64, svuint64_t, svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u64, svuint64_t, svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u64, svuint64_t, svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u64, svuint64_t, svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u64, svuint64_t, svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u64, svuint64_t, svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u64, svuint64_t, svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u64, svuint64_t, svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u64, svuint64_t, svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_u64, svuint64_t, svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f16, svfloat16_t, svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f16, svfloat16_t, svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f16, svfloat16_t, svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f16, svfloat16_t, svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f16, svfloat16_t, svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f16, svfloat16_t, svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f16, svfloat16_t, svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f16, svfloat16_t, svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f16, svfloat16_t, svfloat32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f16, svfloat16_t, svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f32, svfloat32_t, svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f32, svfloat32_t, svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f32, svfloat32_t, svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f32, svfloat32_t, svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f32, svfloat32_t, svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f32, svfloat32_t, svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f32, svfloat32_t, svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f32, svfloat32_t, svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f32, svfloat32_t, svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f32, svfloat32_t, svfloat64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f64, svfloat64_t, svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f64, svfloat64_t, svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f64, svfloat64_t, svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f64, svfloat64_t, svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f64, svfloat64_t, svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f64, svfloat64_t, svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f64, svfloat64_t, svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f64, svfloat64_t, svuint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f64, svfloat64_t, svfloat16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( svreinterpret_f64, svfloat64_t, svfloat32_t)
|
||||
#endif /* defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES) */
|
||||
#elif defined(SIMDE_GENERIC_)
|
||||
#define simde_svreinterpret_f64(op) \
|
||||
(_Generic((op), \
|
||||
simde_svint16_t: simde_svreinterpret_s8_s16, \
|
||||
simde_svint32_t: simde_svreinterpret_s8_s32, \
|
||||
simde_svint64_t: simde_svreinterpret_s8_s64, \
|
||||
simde_svuint8_t: simde_svreinterpret_s8_u8, \
|
||||
simde_svuint16_t: simde_svreinterpret_s8_u16, \
|
||||
simde_svuint32_t: simde_svreinterpret_s8_u32, \
|
||||
simde_svuint64_t: simde_svreinterpret_s8_u64, \
|
||||
simde_svfloat16_t: simde_svreinterpret_s8_f16, \
|
||||
simde_svfloat32_t: simde_svreinterpret_s8_f32, \
|
||||
simde_svfloat64_t: simde_svreinterpret_s8_f64)(op))
|
||||
#define simde_svreinterpret_s8(op) \
|
||||
(_Generic((op), \
|
||||
simde_svint8_t: simde_svreinterpret_s16_s8, \
|
||||
simde_svint32_t: simde_svreinterpret_s16_s32, \
|
||||
simde_svint64_t: simde_svreinterpret_s16_s64, \
|
||||
simde_svuint8_t: simde_svreinterpret_s16_u8, \
|
||||
simde_svuint16_t: simde_svreinterpret_s16_u16, \
|
||||
simde_svuint32_t: simde_svreinterpret_s16_u32, \
|
||||
simde_svuint64_t: simde_svreinterpret_s16_u64, \
|
||||
simde_svfloat16_t: simde_svreinterpret_s16_f16, \
|
||||
simde_svfloat32_t: simde_svreinterpret_s16_f32, \
|
||||
simde_svfloat64_t: simde_svreinterpret_s16_f64)(op))
|
||||
#define simde_svreinterpret_s16(op) \
|
||||
(_Generic((op), \
|
||||
simde_svint8_t: simde_svreinterpret_s32_s8, \
|
||||
simde_svint16_t: simde_svreinterpret_s32_s16, \
|
||||
simde_svint64_t: simde_svreinterpret_s32_s64, \
|
||||
simde_svuint8_t: simde_svreinterpret_s32_u8, \
|
||||
simde_svuint16_t: simde_svreinterpret_s32_u16, \
|
||||
simde_svuint32_t: simde_svreinterpret_s32_u32, \
|
||||
simde_svuint64_t: simde_svreinterpret_s32_u64, \
|
||||
simde_svfloat16_t: simde_svreinterpret_s32_f16, \
|
||||
simde_svfloat32_t: simde_svreinterpret_s32_f32, \
|
||||
simde_svfloat64_t: simde_svreinterpret_s32_f64)(op))
|
||||
#define simde_svreinterpret_s32(op) \
|
||||
(_Generic((op), \
|
||||
simde_svint8_t: simde_svreinterpret_s64_s8, \
|
||||
simde_svint16_t: simde_svreinterpret_s64_s16, \
|
||||
simde_svint32_t: simde_svreinterpret_s64_s32, \
|
||||
simde_svuint8_t: simde_svreinterpret_s64_u8, \
|
||||
simde_svuint16_t: simde_svreinterpret_s64_u16, \
|
||||
simde_svuint32_t: simde_svreinterpret_s64_u32, \
|
||||
simde_svuint64_t: simde_svreinterpret_s64_u64, \
|
||||
simde_svfloat16_t: simde_svreinterpret_s64_f16, \
|
||||
simde_svfloat32_t: simde_svreinterpret_s64_f32, \
|
||||
simde_svfloat64_t: simde_svreinterpret_s64_f64)(op))
|
||||
#define simde_svreinterpret_s64(op) \
|
||||
(_Generic((op), \
|
||||
simde_svint8_t: simde_svreinterpret_u8_s8, \
|
||||
simde_svint16_t: simde_svreinterpret_u8_s16, \
|
||||
simde_svint32_t: simde_svreinterpret_u8_s32, \
|
||||
simde_svint64_t: simde_svreinterpret_u8_s64, \
|
||||
simde_svuint16_t: simde_svreinterpret_u8_u16, \
|
||||
simde_svuint32_t: simde_svreinterpret_u8_u32, \
|
||||
simde_svuint64_t: simde_svreinterpret_u8_u64, \
|
||||
simde_svfloat16_t: simde_svreinterpret_u8_f16, \
|
||||
simde_svfloat32_t: simde_svreinterpret_u8_f32, \
|
||||
simde_svfloat64_t: simde_svreinterpret_u8_f64)(op))
|
||||
#define simde_svreinterpret_u8(op) \
|
||||
(_Generic((op), \
|
||||
simde_svint8_t: simde_svreinterpret_u16_s8, \
|
||||
simde_svint16_t: simde_svreinterpret_u16_s16, \
|
||||
simde_svint32_t: simde_svreinterpret_u16_s32, \
|
||||
simde_svint64_t: simde_svreinterpret_u16_s64, \
|
||||
simde_svuint8_t: simde_svreinterpret_u16_u8, \
|
||||
simde_svuint32_t: simde_svreinterpret_u16_u32, \
|
||||
simde_svuint64_t: simde_svreinterpret_u16_u64, \
|
||||
simde_svfloat16_t: simde_svreinterpret_u16_f16, \
|
||||
simde_svfloat32_t: simde_svreinterpret_u16_f32, \
|
||||
simde_svfloat64_t: simde_svreinterpret_u16_f64)(op))
|
||||
#define simde_svreinterpret_u16(op) \
|
||||
(_Generic((op), \
|
||||
simde_svint8_t: simde_svreinterpret_u32_s8, \
|
||||
simde_svint16_t: simde_svreinterpret_u32_s16, \
|
||||
simde_svint32_t: simde_svreinterpret_u32_s32, \
|
||||
simde_svint64_t: simde_svreinterpret_u32_s64, \
|
||||
simde_svuint8_t: simde_svreinterpret_u32_u8, \
|
||||
simde_svuint16_t: simde_svreinterpret_u32_u16, \
|
||||
simde_svuint64_t: simde_svreinterpret_u32_u64, \
|
||||
simde_svfloat16_t: simde_svreinterpret_u32_f16, \
|
||||
simde_svfloat32_t: simde_svreinterpret_u32_f32, \
|
||||
simde_svfloat64_t: simde_svreinterpret_u32_f64)(op))
|
||||
#define simde_svreinterpret_u32(op) \
|
||||
(_Generic((op), \
|
||||
simde_svint8_t: simde_svreinterpret_u64_s8, \
|
||||
simde_svint16_t: simde_svreinterpret_u64_s16, \
|
||||
simde_svint32_t: simde_svreinterpret_u64_s32, \
|
||||
simde_svint64_t: simde_svreinterpret_u64_s64, \
|
||||
simde_svuint8_t: simde_svreinterpret_u64_u8, \
|
||||
simde_svuint16_t: simde_svreinterpret_u64_u16, \
|
||||
simde_svuint32_t: simde_svreinterpret_u64_u32, \
|
||||
simde_svfloat16_t: simde_svreinterpret_u64_f16, \
|
||||
simde_svfloat32_t: simde_svreinterpret_u64_f32, \
|
||||
simde_svfloat64_t: simde_svreinterpret_u64_f64)(op))
|
||||
#define simde_svreinterpret_u64(op) \
|
||||
(_Generic((op), \
|
||||
simde_svint8_t: simde_svreinterpret_f16_s8, \
|
||||
simde_svint16_t: simde_svreinterpret_f16_s16, \
|
||||
simde_svint32_t: simde_svreinterpret_f16_s32, \
|
||||
simde_svint64_t: simde_svreinterpret_f16_s64, \
|
||||
simde_svuint8_t: simde_svreinterpret_f16_u8, \
|
||||
simde_svuint16_t: simde_svreinterpret_f16_u16, \
|
||||
simde_svuint32_t: simde_svreinterpret_f16_u32, \
|
||||
simde_svuint64_t: simde_svreinterpret_f16_u64, \
|
||||
simde_svfloat32_t: simde_svreinterpret_f16_f32, \
|
||||
simde_svfloat64_t: simde_svreinterpret_f16_f64)(op))
|
||||
#define simde_svreinterpret_f16(op) \
|
||||
(_Generic((op), \
|
||||
simde_svint8_t: simde_svreinterpret_f32_s8, \
|
||||
simde_svint16_t: simde_svreinterpret_f32_s16, \
|
||||
simde_svint32_t: simde_svreinterpret_f32_s32, \
|
||||
simde_svint64_t: simde_svreinterpret_f32_s64, \
|
||||
simde_svuint8_t: simde_svreinterpret_f32_u8, \
|
||||
simde_svuint16_t: simde_svreinterpret_f32_u16, \
|
||||
simde_svuint32_t: simde_svreinterpret_f32_u32, \
|
||||
simde_svuint64_t: simde_svreinterpret_f32_u64, \
|
||||
simde_svfloat16_t: simde_svreinterpret_f32_f16, \
|
||||
simde_svfloat64_t: simde_svreinterpret_f32_f64)(op))
|
||||
#define simde_svreinterpret_f32(op) \
|
||||
(_Generic((op), \
|
||||
simde_svint8_t: simde_svreinterpret_f64_s8, \
|
||||
simde_svint16_t: simde_svreinterpret_f64_s16, \
|
||||
simde_svint32_t: simde_svreinterpret_f64_s32, \
|
||||
simde_svint64_t: simde_svreinterpret_f64_s64, \
|
||||
simde_svuint8_t: simde_svreinterpret_f64_u8, \
|
||||
simde_svuint16_t: simde_svreinterpret_f64_u16, \
|
||||
simde_svuint32_t: simde_svreinterpret_f64_u32, \
|
||||
simde_svuint64_t: simde_svreinterpret_f64_u64, \
|
||||
simde_svfloat16_t: simde_svreinterpret_f64_f16, \
|
||||
simde_svfloat32_t: simde_svreinterpret_f64_f32)(op))
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#define svreinterpret_f64(op) \
|
||||
(_Generic((op), \
|
||||
svint16_t: svreinterpret_s8_s16, \
|
||||
svint32_t: svreinterpret_s8_s32, \
|
||||
svint64_t: svreinterpret_s8_s64, \
|
||||
svuint8_t: svreinterpret_s8_u8, \
|
||||
svuint16_t: svreinterpret_s8_u16, \
|
||||
svuint32_t: svreinterpret_s8_u32, \
|
||||
svuint64_t: svreinterpret_s8_u64, \
|
||||
svfloat16_t: svreinterpret_s8_f16, \
|
||||
svfloat32_t: svreinterpret_s8_f32, \
|
||||
svfloat64_t: svreinterpret_s8_f64)(op))
|
||||
#define svreinterpret_s8(op) \
|
||||
(_Generic((op), \
|
||||
svint8_t: svreinterpret_s16_s8, \
|
||||
svint32_t: svreinterpret_s16_s32, \
|
||||
svint64_t: svreinterpret_s16_s64, \
|
||||
svuint8_t: svreinterpret_s16_u8, \
|
||||
svuint16_t: svreinterpret_s16_u16, \
|
||||
svuint32_t: svreinterpret_s16_u32, \
|
||||
svuint64_t: svreinterpret_s16_u64, \
|
||||
svfloat16_t: svreinterpret_s16_f16, \
|
||||
svfloat32_t: svreinterpret_s16_f32, \
|
||||
svfloat64_t: svreinterpret_s16_f64)(op))
|
||||
#define svreinterpret_s16(op) \
|
||||
(_Generic((op), \
|
||||
svint8_t: svreinterpret_s32_s8, \
|
||||
svint16_t: svreinterpret_s32_s16, \
|
||||
svint64_t: svreinterpret_s32_s64, \
|
||||
svuint8_t: svreinterpret_s32_u8, \
|
||||
svuint16_t: svreinterpret_s32_u16, \
|
||||
svuint32_t: svreinterpret_s32_u32, \
|
||||
svuint64_t: svreinterpret_s32_u64, \
|
||||
svfloat16_t: svreinterpret_s32_f16, \
|
||||
svfloat32_t: svreinterpret_s32_f32, \
|
||||
svfloat64_t: svreinterpret_s32_f64)(op))
|
||||
#define svreinterpret_s32(op) \
|
||||
(_Generic((op), \
|
||||
svint8_t: svreinterpret_s64_s8, \
|
||||
svint16_t: svreinterpret_s64_s16, \
|
||||
svint32_t: svreinterpret_s64_s32, \
|
||||
svuint8_t: svreinterpret_s64_u8, \
|
||||
svuint16_t: svreinterpret_s64_u16, \
|
||||
svuint32_t: svreinterpret_s64_u32, \
|
||||
svuint64_t: svreinterpret_s64_u64, \
|
||||
svfloat16_t: svreinterpret_s64_f16, \
|
||||
svfloat32_t: svreinterpret_s64_f32, \
|
||||
svfloat64_t: svreinterpret_s64_f64)(op))
|
||||
#define svreinterpret_s64(op) \
|
||||
(_Generic((op), \
|
||||
svint8_t: svreinterpret_u8_s8, \
|
||||
svint16_t: svreinterpret_u8_s16, \
|
||||
svint32_t: svreinterpret_u8_s32, \
|
||||
svint64_t: svreinterpret_u8_s64, \
|
||||
svuint16_t: svreinterpret_u8_u16, \
|
||||
svuint32_t: svreinterpret_u8_u32, \
|
||||
svuint64_t: svreinterpret_u8_u64, \
|
||||
svfloat16_t: svreinterpret_u8_f16, \
|
||||
svfloat32_t: svreinterpret_u8_f32, \
|
||||
svfloat64_t: svreinterpret_u8_f64)(op))
|
||||
#define svreinterpret_u8(op) \
|
||||
(_Generic((op), \
|
||||
svint8_t: svreinterpret_u16_s8, \
|
||||
svint16_t: svreinterpret_u16_s16, \
|
||||
svint32_t: svreinterpret_u16_s32, \
|
||||
svint64_t: svreinterpret_u16_s64, \
|
||||
svuint8_t: svreinterpret_u16_u8, \
|
||||
svuint32_t: svreinterpret_u16_u32, \
|
||||
svuint64_t: svreinterpret_u16_u64, \
|
||||
svfloat16_t: svreinterpret_u16_f16, \
|
||||
svfloat32_t: svreinterpret_u16_f32, \
|
||||
svfloat64_t: svreinterpret_u16_f64)(op))
|
||||
#define svreinterpret_u16(op) \
|
||||
(_Generic((op), \
|
||||
svint8_t: svreinterpret_u32_s8, \
|
||||
svint16_t: svreinterpret_u32_s16, \
|
||||
svint32_t: svreinterpret_u32_s32, \
|
||||
svint64_t: svreinterpret_u32_s64, \
|
||||
svuint8_t: svreinterpret_u32_u8, \
|
||||
svuint16_t: svreinterpret_u32_u16, \
|
||||
svuint64_t: svreinterpret_u32_u64, \
|
||||
svfloat16_t: svreinterpret_u32_f16, \
|
||||
svfloat32_t: svreinterpret_u32_f32, \
|
||||
svfloat64_t: svreinterpret_u32_f64)(op))
|
||||
#define svreinterpret_u32(op) \
|
||||
(_Generic((op), \
|
||||
svint8_t: svreinterpret_u64_s8, \
|
||||
svint16_t: svreinterpret_u64_s16, \
|
||||
svint32_t: svreinterpret_u64_s32, \
|
||||
svint64_t: svreinterpret_u64_s64, \
|
||||
svuint8_t: svreinterpret_u64_u8, \
|
||||
svuint16_t: svreinterpret_u64_u16, \
|
||||
svuint32_t: svreinterpret_u64_u32, \
|
||||
svfloat16_t: svreinterpret_u64_f16, \
|
||||
svfloat32_t: svreinterpret_u64_f32, \
|
||||
svfloat64_t: svreinterpret_u64_f64)(op))
|
||||
#define svreinterpret_u64(op) \
|
||||
(_Generic((op), \
|
||||
svint8_t: svreinterpret_f16_s8, \
|
||||
svint16_t: svreinterpret_f16_s16, \
|
||||
svint32_t: svreinterpret_f16_s32, \
|
||||
svint64_t: svreinterpret_f16_s64, \
|
||||
svuint8_t: svreinterpret_f16_u8, \
|
||||
svuint16_t: svreinterpret_f16_u16, \
|
||||
svuint32_t: svreinterpret_f16_u32, \
|
||||
svuint64_t: svreinterpret_f16_u64, \
|
||||
svfloat32_t: svreinterpret_f16_f32, \
|
||||
svfloat64_t: svreinterpret_f16_f64)(op))
|
||||
#define svreinterpret_f16(op) \
|
||||
(_Generic((op), \
|
||||
svint8_t: svreinterpret_f32_s8, \
|
||||
svint16_t: svreinterpret_f32_s16, \
|
||||
svint32_t: svreinterpret_f32_s32, \
|
||||
svint64_t: svreinterpret_f32_s64, \
|
||||
svuint8_t: svreinterpret_f32_u8, \
|
||||
svuint16_t: svreinterpret_f32_u16, \
|
||||
svuint32_t: svreinterpret_f32_u32, \
|
||||
svuint64_t: svreinterpret_f32_u64, \
|
||||
svfloat16_t: svreinterpret_f32_f16, \
|
||||
svfloat64_t: svreinterpret_f32_f64)(op))
|
||||
#define svreinterpret_f32(op) \
|
||||
(_Generic((op), \
|
||||
svint8_t: svreinterpret_f64_s8, \
|
||||
svint16_t: svreinterpret_f64_s16, \
|
||||
svint32_t: svreinterpret_f64_s32, \
|
||||
svint64_t: svreinterpret_f64_s64, \
|
||||
svuint8_t: svreinterpret_f64_u8, \
|
||||
svuint16_t: svreinterpret_f64_u16, \
|
||||
svuint32_t: svreinterpret_f64_u32, \
|
||||
svuint64_t: svreinterpret_f64_u64, \
|
||||
svfloat16_t: svreinterpret_f64_f16, \
|
||||
svfloat32_t: svreinterpret_f64_f32)(op))
|
||||
#endif /* defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES) */
|
||||
#endif
|
||||
|
||||
HEDLEY_DIAGNOSTIC_POP
|
||||
|
||||
#endif /* SIMDE_ARM_SVE_REINTERPRET_H */
|
||||
@@ -0,0 +1,626 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use, copy,
|
||||
* modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
* of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Copyright:
|
||||
* 2021 Evan Nemerson <evan@nemerson.com>
|
||||
*/
|
||||
|
||||
#if !defined(SIMDE_ARM_SVE_SEL_H)
|
||||
#define SIMDE_ARM_SVE_SEL_H
|
||||
|
||||
#include "types.h"
|
||||
#include "reinterpret.h"
|
||||
|
||||
HEDLEY_DIAGNOSTIC_PUSH
|
||||
SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint8_t
|
||||
simde_x_svsel_s8_z(simde_svbool_t pg, simde_svint8_t op1) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svand_s8_z(pg, op1, op1);
|
||||
#else
|
||||
simde_svint8_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vandq_s8(pg.neon_i8, op1.neon);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_maskz_mov_epi8(simde_svbool_to_mmask64(pg), op1.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_maskz_mov_epi8(simde_svbool_to_mmask32(pg), op1.m256i[0]);
|
||||
#elif defined(SIMDE_X86_AVX2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m256i) / sizeof(r.m256i[0])) ; i++) {
|
||||
r.m256i[i] = _mm256_and_si256(pg.m256i[i], op1.m256i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_and_si128(pg.m128i[i], op1.m128i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
|
||||
r.altivec = vec_and(pg.altivec_b8, op1.altivec);
|
||||
#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec = pg.values_i8 & op1.altivec;
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_v128_and(pg.v128, op1.v128);
|
||||
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
|
||||
r.values = pg.values_i8 & op1.values;
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = pg.values_i8[i] & op1.values[i];
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint8_t
|
||||
simde_svsel_s8(simde_svbool_t pg, simde_svint8_t op1, simde_svint8_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svsel_s8(pg, op1, op2);
|
||||
#else
|
||||
simde_svint8_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vbslq_s8(pg.neon_u8, op1.neon, op2.neon);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_mask_mov_epi8(op2.m512i, simde_svbool_to_mmask64(pg), op1.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_mask_mov_epi8(op2.m256i[0], simde_svbool_to_mmask32(pg), op1.m256i[0]);
|
||||
#elif defined(SIMDE_X86_AVX2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m256i) / sizeof(r.m256i[0])) ; i++) {
|
||||
r.m256i[i] = _mm256_blendv_epi8(op2.m256i[i], op1.m256i[i], pg.m256i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE4_1_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_blendv_epi8(op2.m128i[i], op1.m128i[i], pg.m128i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_or_si128(_mm_and_si128(pg.m128i[i], op1.m128i[i]), _mm_andnot_si128(pg.m128i[i], op2.m128i[i]));
|
||||
}
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec = vec_sel(op2.altivec, op1.altivec, pg.altivec_b8);
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_v128_bitselect(op1.v128, op2.v128, pg.v128);
|
||||
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
|
||||
r.values = (pg.values_i8 & op1.values) | (~pg.values_i8 & op2.values);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = (pg.values_i8[i] & op1.values[i]) | (~pg.values_i8[i] & op2.values[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svsel_s8
|
||||
#define svsel_s8(pg, op1, op2) simde_svsel_s8(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint16_t
|
||||
simde_x_svsel_s16_z(simde_svbool_t pg, simde_svint16_t op1) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svand_s16_z(pg, op1, op1);
|
||||
#else
|
||||
simde_svint16_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vandq_s16(pg.neon_i16, op1.neon);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_maskz_mov_epi16(simde_svbool_to_mmask32(pg), op1.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_maskz_mov_epi16(simde_svbool_to_mmask16(pg), op1.m256i[0]);
|
||||
#elif defined(SIMDE_X86_AVX2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m256i) / sizeof(r.m256i[0])) ; i++) {
|
||||
r.m256i[i] = _mm256_and_si256(pg.m256i[i], op1.m256i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_and_si128(pg.m128i[i], op1.m128i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
|
||||
r.altivec = vec_and(pg.altivec_b16, op1.altivec);
|
||||
#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec = pg.values_i16 & op1.altivec;
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_v128_and(pg.v128, op1.v128);
|
||||
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
|
||||
r.values = pg.values_i16 & op1.values;
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = pg.values_i16[i] & op1.values[i];
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint16_t
|
||||
simde_svsel_s16(simde_svbool_t pg, simde_svint16_t op1, simde_svint16_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svsel_s16(pg, op1, op2);
|
||||
#else
|
||||
simde_svint16_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vbslq_s16(pg.neon_u16, op1.neon, op2.neon);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_mask_mov_epi16(op2.m512i, simde_svbool_to_mmask32(pg), op1.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_mask_mov_epi16(op2.m256i[0], simde_svbool_to_mmask16(pg), op1.m256i[0]);
|
||||
#elif defined(SIMDE_X86_AVX2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m256i) / sizeof(r.m256i[0])) ; i++) {
|
||||
r.m256i[i] = _mm256_blendv_epi8(op2.m256i[i], op1.m256i[i], pg.m256i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE4_1_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_blendv_epi8(op2.m128i[i], op1.m128i[i], pg.m128i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_or_si128(_mm_and_si128(pg.m128i[i], op1.m128i[i]), _mm_andnot_si128(pg.m128i[i], op2.m128i[i]));
|
||||
}
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec = vec_sel(op2.altivec, op1.altivec, pg.altivec_b16);
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_v128_bitselect(op1.v128, op2.v128, pg.v128);
|
||||
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
|
||||
r.values = (pg.values_i16 & op1.values) | (~pg.values_i16 & op2.values);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = (pg.values_i16[i] & op1.values[i]) | (~pg.values_i16[i] & op2.values[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svsel_s16
|
||||
#define svsel_s16(pg, op1, op2) simde_svsel_s16(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint32_t
|
||||
simde_x_svsel_s32_z(simde_svbool_t pg, simde_svint32_t op1) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svand_s32_z(pg, op1, op1);
|
||||
#else
|
||||
simde_svint32_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vandq_s32(pg.neon_i32, op1.neon);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_maskz_mov_epi32(simde_svbool_to_mmask16(pg), op1.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_maskz_mov_epi32(simde_svbool_to_mmask8(pg), op1.m256i[0]);
|
||||
#elif defined(SIMDE_X86_AVX2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m256i) / sizeof(r.m256i[0])) ; i++) {
|
||||
r.m256i[i] = _mm256_and_si256(pg.m256i[i], op1.m256i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_and_si128(pg.m128i[i], op1.m128i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
|
||||
r.altivec = vec_and(pg.altivec_b32, op1.altivec);
|
||||
#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec = pg.values_i32 & op1.altivec;
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_v128_and(pg.v128, op1.v128);
|
||||
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
|
||||
r.values = pg.values_i32 & op1.values;
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = pg.values_i32[i] & op1.values[i];
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint32_t
|
||||
simde_svsel_s32(simde_svbool_t pg, simde_svint32_t op1, simde_svint32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svsel_s32(pg, op1, op2);
|
||||
#else
|
||||
simde_svint32_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vbslq_s32(pg.neon_u32, op1.neon, op2.neon);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_mask_mov_epi32(op2.m512i, simde_svbool_to_mmask16(pg), op1.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_mask_mov_epi32(op2.m256i[0], simde_svbool_to_mmask8(pg), op1.m256i[0]);
|
||||
#elif defined(SIMDE_X86_AVX2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m256i) / sizeof(r.m256i[0])) ; i++) {
|
||||
r.m256i[i] = _mm256_blendv_epi8(op2.m256i[i], op1.m256i[i], pg.m256i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE4_1_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_blendv_epi8(op2.m128i[i], op1.m128i[i], pg.m128i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_or_si128(_mm_and_si128(pg.m128i[i], op1.m128i[i]), _mm_andnot_si128(pg.m128i[i], op2.m128i[i]));
|
||||
}
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec = vec_sel(op2.altivec, op1.altivec, pg.altivec_b32);
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_v128_bitselect(op1.v128, op2.v128, pg.v128);
|
||||
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
|
||||
r.values = (pg.values_i32 & op1.values) | (~pg.values_i32 & op2.values);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = (pg.values_i32[i] & op1.values[i]) | (~pg.values_i32[i] & op2.values[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svsel_s32
|
||||
#define svsel_s32(pg, op1, op2) simde_svsel_s32(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint64_t
|
||||
simde_x_svsel_s64_z(simde_svbool_t pg, simde_svint64_t op1) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svand_s64_z(pg, op1, op1);
|
||||
#else
|
||||
simde_svint64_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vandq_s64(pg.neon_i64, op1.neon);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_maskz_mov_epi64(simde_svbool_to_mmask8(pg), op1.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_maskz_mov_epi64(simde_svbool_to_mmask4(pg), op1.m256i[0]);
|
||||
#elif defined(SIMDE_X86_AVX2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m256i) / sizeof(r.m256i[0])) ; i++) {
|
||||
r.m256i[i] = _mm256_and_si256(pg.m256i[i], op1.m256i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_and_si128(pg.m128i[i], op1.m128i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_POWER_ALTIVEC_P7_NATIVE)
|
||||
r.altivec = vec_and(pg.altivec_b64, op1.altivec);
|
||||
#elif defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
r.altivec = HEDLEY_REINTERPRET_CAST(__typeof__(op1.altivec), pg.values_i64) & op1.altivec;
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_v128_and(pg.v128, op1.v128);
|
||||
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
|
||||
r.values = pg.values_i64 & op1.values;
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = pg.values_i64[i] & op1.values[i];
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svint64_t
|
||||
simde_svsel_s64(simde_svbool_t pg, simde_svint64_t op1, simde_svint64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svsel_s64(pg, op1, op2);
|
||||
#else
|
||||
simde_svint64_t r;
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
r.neon = vbslq_s64(pg.neon_u64, op1.neon, op2.neon);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m512i = _mm512_mask_mov_epi64(op2.m512i, simde_svbool_to_mmask8(pg), op1.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
r.m256i[0] = _mm256_mask_mov_epi64(op2.m256i[0], simde_svbool_to_mmask4(pg), op1.m256i[0]);
|
||||
#elif defined(SIMDE_X86_AVX2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m256i) / sizeof(r.m256i[0])) ; i++) {
|
||||
r.m256i[i] = _mm256_blendv_epi8(op2.m256i[i], op1.m256i[i], pg.m256i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE4_1_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_blendv_epi8(op2.m128i[i], op1.m128i[i], pg.m128i[i]);
|
||||
}
|
||||
#elif defined(SIMDE_X86_SSE2_NATIVE)
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.m128i) / sizeof(r.m128i[0])) ; i++) {
|
||||
r.m128i[i] = _mm_or_si128(_mm_and_si128(pg.m128i[i], op1.m128i[i]), _mm_andnot_si128(pg.m128i[i], op2.m128i[i]));
|
||||
}
|
||||
#elif (defined(SIMDE_POWER_ALTIVEC_P7_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)) && !defined(SIMDE_BUG_CLANG_46770)
|
||||
r.altivec = vec_sel(op2.altivec, op1.altivec, pg.altivec_b64);
|
||||
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
r.v128 = wasm_v128_bitselect(op1.v128, op2.v128, pg.v128);
|
||||
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
|
||||
r.values = (pg.values_i64 & op1.values) | (~pg.values_i64 & op2.values);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, sizeof(r.values) / sizeof(r.values[0])) ; i++) {
|
||||
r.values[i] = (pg.values_i64[i] & op1.values[i]) | (~pg.values_i64[i] & op2.values[i]);
|
||||
}
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svsel_s64
|
||||
#define svsel_s64(pg, op1, op2) simde_svsel_s64(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint8_t
|
||||
simde_x_svsel_u8_z(simde_svbool_t pg, simde_svuint8_t op1) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svand_u8_z(pg, op1, op1);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && ((SIMDE_ARM_SVE_VECTOR_SIZE >= 512) || defined(SIMDE_X86_AVX512VL_NATIVE)) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
simde_svuint8_t r;
|
||||
|
||||
#if SIMDE_ARM_SVE_VECTOR_SIZE >= 512
|
||||
r.m512i = _mm512_maskz_mov_epi8(simde_svbool_to_mmask64(pg), op1.m512i);
|
||||
#else
|
||||
r.m256i[0] = _mm256_maskz_mov_epi8(simde_svbool_to_mmask32(pg), op1.m256i[0]);
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#else
|
||||
return simde_svreinterpret_u8_s8(simde_x_svsel_s8_z(pg, simde_svreinterpret_s8_u8(op1)));
|
||||
#endif
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint8_t
|
||||
simde_svsel_u8(simde_svbool_t pg, simde_svuint8_t op1, simde_svuint8_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svsel_u8(pg, op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && ((SIMDE_ARM_SVE_VECTOR_SIZE >= 512) || defined(SIMDE_X86_AVX512VL_NATIVE)) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
simde_svuint8_t r;
|
||||
|
||||
#if SIMDE_ARM_SVE_VECTOR_SIZE >= 512
|
||||
r.m512i = _mm512_mask_mov_epi8(op2.m512i, simde_svbool_to_mmask64(pg), op1.m512i);
|
||||
#else
|
||||
r.m256i[0] = _mm256_mask_mov_epi8(op2.m256i[0], simde_svbool_to_mmask32(pg), op1.m256i[0]);
|
||||
#endif
|
||||
|
||||
return r;
|
||||
#else
|
||||
return simde_svreinterpret_u8_s8(simde_svsel_s8(pg, simde_svreinterpret_s8_u8(op1), simde_svreinterpret_s8_u8(op2)));
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svsel_u8
|
||||
#define svsel_u8(pg, op1, op2) simde_svsel_u8(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint16_t
|
||||
simde_x_svsel_u16_z(simde_svbool_t pg, simde_svuint16_t op1) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svand_u16_z(pg, op1, op1);
|
||||
#else
|
||||
return simde_svreinterpret_u16_s16(simde_x_svsel_s16_z(pg, simde_svreinterpret_s16_u16(op1)));
|
||||
#endif
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint16_t
|
||||
simde_svsel_u16(simde_svbool_t pg, simde_svuint16_t op1, simde_svuint16_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svsel_u16(pg, op1, op2);
|
||||
#else
|
||||
return simde_svreinterpret_u16_s16(simde_svsel_s16(pg, simde_svreinterpret_s16_u16(op1), simde_svreinterpret_s16_u16(op2)));
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svsel_u16
|
||||
#define svsel_u16(pg, op1, op2) simde_svsel_u16(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint32_t
|
||||
simde_x_svsel_u32_z(simde_svbool_t pg, simde_svuint32_t op1) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svand_u32_z(pg, op1, op1);
|
||||
#else
|
||||
return simde_svreinterpret_u32_s32(simde_x_svsel_s32_z(pg, simde_svreinterpret_s32_u32(op1)));
|
||||
#endif
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint32_t
|
||||
simde_svsel_u32(simde_svbool_t pg, simde_svuint32_t op1, simde_svuint32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svsel_u32(pg, op1, op2);
|
||||
#else
|
||||
return simde_svreinterpret_u32_s32(simde_svsel_s32(pg, simde_svreinterpret_s32_u32(op1), simde_svreinterpret_s32_u32(op2)));
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svsel_u32
|
||||
#define svsel_u32(pg, op1, op2) simde_svsel_u32(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint64_t
|
||||
simde_x_svsel_u64_z(simde_svbool_t pg, simde_svuint64_t op1) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svand_u64_z(pg, op1, op1);
|
||||
#else
|
||||
return simde_svreinterpret_u64_s64(simde_x_svsel_s64_z(pg, simde_svreinterpret_s64_u64(op1)));
|
||||
#endif
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svuint64_t
|
||||
simde_svsel_u64(simde_svbool_t pg, simde_svuint64_t op1, simde_svuint64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svsel_u64(pg, op1, op2);
|
||||
#else
|
||||
return simde_svreinterpret_u64_s64(simde_svsel_s64(pg, simde_svreinterpret_s64_u64(op1), simde_svreinterpret_s64_u64(op2)));
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svsel_u64
|
||||
#define svsel_u64(pg, op1, op2) simde_svsel_u64(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svfloat32_t
|
||||
simde_x_svsel_f32_z(simde_svbool_t pg, simde_svfloat32_t op1) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return simde_svreinterpret_f32_s32(svand_s32_z(pg, simde_svreinterpret_s32_f32(op1), simde_svreinterpret_s32_f32(op1)));
|
||||
#else
|
||||
return simde_svreinterpret_f32_s32(simde_x_svsel_s32_z(pg, simde_svreinterpret_s32_f32(op1)));
|
||||
#endif
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svfloat32_t
|
||||
simde_svsel_f32(simde_svbool_t pg, simde_svfloat32_t op1, simde_svfloat32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svsel_f32(pg, op1, op2);
|
||||
#else
|
||||
return simde_svreinterpret_f32_s32(simde_svsel_s32(pg, simde_svreinterpret_s32_f32(op1), simde_svreinterpret_s32_f32(op2)));
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svsel_f32
|
||||
#define svsel_f32(pg, op1, op2) simde_svsel_f32(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svfloat64_t
|
||||
simde_x_svsel_f64_z(simde_svbool_t pg, simde_svfloat64_t op1) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return simde_svreinterpret_f64_s64(svand_s64_z(pg, simde_svreinterpret_s64_f64(op1), simde_svreinterpret_s64_f64(op1)));
|
||||
#else
|
||||
return simde_svreinterpret_f64_s64(simde_x_svsel_s64_z(pg, simde_svreinterpret_s64_f64(op1)));
|
||||
#endif
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svfloat64_t
|
||||
simde_svsel_f64(simde_svbool_t pg, simde_svfloat64_t op1, simde_svfloat64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svsel_f64(pg, op1, op2);
|
||||
#else
|
||||
return simde_svreinterpret_f64_s64(simde_svsel_s64(pg, simde_svreinterpret_s64_f64(op1), simde_svreinterpret_s64_f64(op2)));
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svsel_f64
|
||||
#define svsel_f64(pg, op1, op2) simde_svsel_f64(pg, op1, op2)
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_x_svsel_z(simde_svbool_t pg, simde_svint8_t op1) { return simde_x_svsel_s8_z (pg, op1); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_x_svsel_z(simde_svbool_t pg, simde_svint16_t op1) { return simde_x_svsel_s16_z(pg, op1); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_x_svsel_z(simde_svbool_t pg, simde_svint32_t op1) { return simde_x_svsel_s32_z(pg, op1); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_x_svsel_z(simde_svbool_t pg, simde_svint64_t op1) { return simde_x_svsel_s64_z(pg, op1); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_x_svsel_z(simde_svbool_t pg, simde_svuint8_t op1) { return simde_x_svsel_u8_z (pg, op1); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_x_svsel_z(simde_svbool_t pg, simde_svuint16_t op1) { return simde_x_svsel_u16_z(pg, op1); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_x_svsel_z(simde_svbool_t pg, simde_svuint32_t op1) { return simde_x_svsel_u32_z(pg, op1); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_x_svsel_z(simde_svbool_t pg, simde_svuint64_t op1) { return simde_x_svsel_u64_z(pg, op1); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_x_svsel_z(simde_svbool_t pg, simde_svfloat32_t op1) { return simde_x_svsel_f32_z(pg, op1); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_x_svsel_z(simde_svbool_t pg, simde_svfloat64_t op1) { return simde_x_svsel_f64_z(pg, op1); }
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint8_t simde_svsel(simde_svbool_t pg, simde_svint8_t op1, simde_svint8_t op2) { return simde_svsel_s8 (pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint16_t simde_svsel(simde_svbool_t pg, simde_svint16_t op1, simde_svint16_t op2) { return simde_svsel_s16(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint32_t simde_svsel(simde_svbool_t pg, simde_svint32_t op1, simde_svint32_t op2) { return simde_svsel_s32(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svint64_t simde_svsel(simde_svbool_t pg, simde_svint64_t op1, simde_svint64_t op2) { return simde_svsel_s64(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint8_t simde_svsel(simde_svbool_t pg, simde_svuint8_t op1, simde_svuint8_t op2) { return simde_svsel_u8 (pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint16_t simde_svsel(simde_svbool_t pg, simde_svuint16_t op1, simde_svuint16_t op2) { return simde_svsel_u16(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint32_t simde_svsel(simde_svbool_t pg, simde_svuint32_t op1, simde_svuint32_t op2) { return simde_svsel_u32(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svuint64_t simde_svsel(simde_svbool_t pg, simde_svuint64_t op1, simde_svuint64_t op2) { return simde_svsel_u64(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat32_t simde_svsel(simde_svbool_t pg, simde_svfloat32_t op1, simde_svfloat32_t op2) { return simde_svsel_f32(pg, op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svfloat64_t simde_svsel(simde_svbool_t pg, simde_svfloat64_t op1, simde_svfloat64_t op2) { return simde_svsel_f64(pg, op1, op2); }
|
||||
#elif defined(SIMDE_GENERIC_)
|
||||
#define simde_x_svsel_z(pg, op1) \
|
||||
(SIMDE_GENERIC_((op1), \
|
||||
simde_svint8_t: simde_x_svsel_s8_z, \
|
||||
simde_svint16_t: simde_x_svsel_s16_z, \
|
||||
simde_svint32_t: simde_x_svsel_s32_z, \
|
||||
simde_svint64_t: simde_x_svsel_s64_z, \
|
||||
simde_svuint8_t: simde_x_svsel_u8_z, \
|
||||
simde_svuint16_t: simde_x_svsel_u16_z, \
|
||||
simde_svuint32_t: simde_x_svsel_u32_z, \
|
||||
simde_svuint64_t: simde_x_svsel_u64_z, \
|
||||
simde_svfloat32_t: simde_x_svsel_f32_z, \
|
||||
simde_svfloat64_t: simde_x_svsel_f64_z)((pg), (op1)))
|
||||
|
||||
#define simde_svsel(pg, op1, op2) \
|
||||
(SIMDE_GENERIC_((op1), \
|
||||
simde_svint8_t: simde_svsel_s8, \
|
||||
simde_svint16_t: simde_svsel_s16, \
|
||||
simde_svint32_t: simde_svsel_s32, \
|
||||
simde_svint64_t: simde_svsel_s64, \
|
||||
simde_svuint8_t: simde_svsel_u8, \
|
||||
simde_svuint16_t: simde_svsel_u16, \
|
||||
simde_svuint32_t: simde_svsel_u32, \
|
||||
simde_svuint64_t: simde_svsel_u64, \
|
||||
simde_svfloat32_t: simde_svsel_f32, \
|
||||
simde_svfloat64_t: simde_svsel_f64)((pg), (op1), (op2)))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef svsel
|
||||
#define svsel(pg, op1) simde_svsel((pg), (op1))
|
||||
#endif
|
||||
|
||||
HEDLEY_DIAGNOSTIC_POP
|
||||
|
||||
#endif /* SIMDE_ARM_SVE_SEL_H */
|
||||
@@ -0,0 +1,307 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use, copy,
|
||||
* modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
* of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Copyright:
|
||||
* 2021 Evan Nemerson <evan@nemerson.com>
|
||||
*/
|
||||
|
||||
#if !defined(SIMDE_ARM_SVE_ST1_H)
|
||||
#define SIMDE_ARM_SVE_ST1_H
|
||||
|
||||
#include "types.h"
|
||||
|
||||
HEDLEY_DIAGNOSTIC_PUSH
|
||||
SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
void
|
||||
simde_svst1_s8(simde_svbool_t pg, int8_t * base, simde_svint8_t data) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
svst1_s8(pg, base, data);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm512_mask_storeu_epi8(base, simde_svbool_to_mmask64(pg), data.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm256_mask_storeu_epi8(base, simde_svbool_to_mmask32(pg), data.m256i[0]);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntb()) ; i++) {
|
||||
if (pg.values_i8[i]) {
|
||||
base[i] = data.values[i];
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svst1_s8
|
||||
#define svst1_s8(pg, base, data) simde_svst1_s8((pg), (base), (data))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
void
|
||||
simde_svst1_s16(simde_svbool_t pg, int16_t * base, simde_svint16_t data) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
svst1_s16(pg, base, data);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm512_mask_storeu_epi16(base, simde_svbool_to_mmask32(pg), data.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm256_mask_storeu_epi16(base, simde_svbool_to_mmask16(pg), data.m256i[0]);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcnth()) ; i++) {
|
||||
if (pg.values_i16[i]) {
|
||||
base[i] = data.values[i];
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svst1_s16
|
||||
#define svst1_s16(pg, base, data) simde_svst1_s16((pg), (base), (data))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
void
|
||||
simde_svst1_s32(simde_svbool_t pg, int32_t * base, simde_svint32_t data) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
svst1_s32(pg, base, data);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm512_mask_storeu_epi32(base, simde_svbool_to_mmask16(pg), data.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm256_mask_storeu_epi32(base, simde_svbool_to_mmask8(pg), data.m256i[0]);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntw()) ; i++) {
|
||||
if (pg.values_i32[i]) {
|
||||
base[i] = data.values[i];
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svst1_s32
|
||||
#define svst1_s32(pg, base, data) simde_svst1_s32((pg), (base), (data))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
void
|
||||
simde_svst1_s64(simde_svbool_t pg, int64_t * base, simde_svint64_t data) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
svst1_s64(pg, base, data);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm512_mask_storeu_epi64(base, simde_svbool_to_mmask8(pg), data.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm256_mask_storeu_epi64(base, simde_svbool_to_mmask4(pg), data.m256i[0]);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntd()) ; i++) {
|
||||
if (pg.values_i64[i]) {
|
||||
base[i] = data.values[i];
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svst1_s64
|
||||
#define svst1_s64(pg, base, data) simde_svst1_s64((pg), (base), (data))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
void
|
||||
simde_svst1_u8(simde_svbool_t pg, uint8_t * base, simde_svuint8_t data) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
svst1_u8(pg, base, data);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm512_mask_storeu_epi8(base, simde_svbool_to_mmask64(pg), data.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm256_mask_storeu_epi8(base, simde_svbool_to_mmask32(pg), data.m256i[0]);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntb()) ; i++) {
|
||||
if (pg.values_u8[i]) {
|
||||
base[i] = data.values[i];
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svst1_u8
|
||||
#define svst1_u8(pg, base, data) simde_svst1_u8((pg), (base), (data))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
void
|
||||
simde_svst1_u16(simde_svbool_t pg, uint16_t * base, simde_svuint16_t data) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
svst1_u16(pg, base, data);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm512_mask_storeu_epi16(base, simde_svbool_to_mmask32(pg), data.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm256_mask_storeu_epi16(base, simde_svbool_to_mmask16(pg), data.m256i[0]);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcnth()) ; i++) {
|
||||
if (pg.values_u16[i]) {
|
||||
base[i] = data.values[i];
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svst1_u16
|
||||
#define svst1_u16(pg, base, data) simde_svst1_u16((pg), (base), (data))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
void
|
||||
simde_svst1_u32(simde_svbool_t pg, uint32_t * base, simde_svuint32_t data) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
svst1_u32(pg, base, data);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm512_mask_storeu_epi32(base, simde_svbool_to_mmask16(pg), data.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm256_mask_storeu_epi32(base, simde_svbool_to_mmask8(pg), data.m256i[0]);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntw()) ; i++) {
|
||||
if (pg.values_u32[i]) {
|
||||
base[i] = data.values[i];
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svst1_u32
|
||||
#define svst1_u32(pg, base, data) simde_svst1_u32((pg), (base), (data))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
void
|
||||
simde_svst1_u64(simde_svbool_t pg, uint64_t * base, simde_svuint64_t data) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
svst1_u64(pg, base, data);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm512_mask_storeu_epi64(base, simde_svbool_to_mmask8(pg), data.m512i);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm256_mask_storeu_epi64(base, simde_svbool_to_mmask4(pg), data.m256i[0]);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntd()) ; i++) {
|
||||
if (pg.values_u64[i]) {
|
||||
base[i] = data.values[i];
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svst1_u64
|
||||
#define svst1_u64(pg, base, data) simde_svst1_u64((pg), (base), (data))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
void
|
||||
simde_svst1_f32(simde_svbool_t pg, simde_float32 * base, simde_svfloat32_t data) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
svst1_f32(pg, base, data);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm512_mask_storeu_ps(base, simde_svbool_to_mmask16(pg), data.m512);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm256_mask_storeu_ps(base, simde_svbool_to_mmask8(pg), data.m256[0]);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntw()) ; i++) {
|
||||
if (pg.values_i32[i]) {
|
||||
base[i] = data.values[i];
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svst1_f32
|
||||
#define svst1_f32(pg, base, data) simde_svst1_f32((pg), (base), (data))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
void
|
||||
simde_svst1_f64(simde_svbool_t pg, simde_float64 * base, simde_svfloat64_t data) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
svst1_f64(pg, base, data);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm512_mask_storeu_pd(base, simde_svbool_to_mmask8(pg), data.m512d);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
_mm256_mask_storeu_pd(base, simde_svbool_to_mmask4(pg), data.m256d[0]);
|
||||
#else
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntd()) ; i++) {
|
||||
if (pg.values_i64[i]) {
|
||||
base[i] = data.values[i];
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svst1_f64
|
||||
#define svst1_f64(pg, base, data) simde_svst1_f64((pg), (base), (data))
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
SIMDE_FUNCTION_ATTRIBUTES void simde_svst1(simde_svbool_t pg, int8_t * base, simde_svint8_t data) { simde_svst1_s8 (pg, base, data); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES void simde_svst1(simde_svbool_t pg, int16_t * base, simde_svint16_t data) { simde_svst1_s16(pg, base, data); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES void simde_svst1(simde_svbool_t pg, int32_t * base, simde_svint32_t data) { simde_svst1_s32(pg, base, data); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES void simde_svst1(simde_svbool_t pg, int64_t * base, simde_svint64_t data) { simde_svst1_s64(pg, base, data); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES void simde_svst1(simde_svbool_t pg, uint8_t * base, simde_svuint8_t data) { simde_svst1_u8 (pg, base, data); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES void simde_svst1(simde_svbool_t pg, uint16_t * base, simde_svuint16_t data) { simde_svst1_u16(pg, base, data); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES void simde_svst1(simde_svbool_t pg, uint32_t * base, simde_svuint32_t data) { simde_svst1_u32(pg, base, data); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES void simde_svst1(simde_svbool_t pg, uint64_t * base, simde_svuint64_t data) { simde_svst1_u64(pg, base, data); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES void simde_svst1(simde_svbool_t pg, simde_float32 * base, simde_svfloat32_t data) { simde_svst1_f32(pg, base, data); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES void simde_svst1(simde_svbool_t pg, simde_float64 * base, simde_svfloat64_t data) { simde_svst1_f64(pg, base, data); }
|
||||
#elif defined(SIMDE_GENERIC_)
|
||||
#define simde_svst1(pg, base, data) \
|
||||
(SIMDE_GENERIC_((data), \
|
||||
simde_svint8_t: simde_svst1_s8 , \
|
||||
simde_svint16_t: simde_svst1_s16, \
|
||||
simde_svint32_t: simde_svst1_s32, \
|
||||
simde_svint64_t: simde_svst1_s64, \
|
||||
simde_svuint8_t: simde_svst1_u8 , \
|
||||
simde_svuint16_t: simde_svst1_u16, \
|
||||
simde_svuint32_t: simde_svst1_u32, \
|
||||
simde_svuint64_t: simde_svst1_u64, \
|
||||
simde_svfloat32_t: simde_svst1_f32, \
|
||||
simde_svfloat64_t: simde_svst1_f64)((pg), (base), (data)))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef svst1
|
||||
#define svst1(pg, base, data) simde_svst1((pg), (base), (data))
|
||||
#endif
|
||||
|
||||
HEDLEY_DIAGNOSTIC_POP
|
||||
|
||||
#endif /* SIMDE_ARM_SVE_ST1_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,915 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use, copy,
|
||||
* modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
* of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Copyright:
|
||||
* 2021 Evan Nemerson <evan@nemerson.com>
|
||||
*/
|
||||
|
||||
/* TODO: SVE2 is going to be a bit awkward with this setup. We currently
|
||||
* either use SVE vectors or assume that the vector length is known at
|
||||
* compile-time. For CPUs which provide SVE but not SVE2 we're going
|
||||
* to be getting scalable vectors, so we may need to loop through them.
|
||||
*
|
||||
* Currently I'm thinking we'll have a separate function for non-SVE
|
||||
* types. We can call that function in a loop from an SVE version,
|
||||
* and we can call it once from a resolver.
|
||||
*
|
||||
* Unfortunately this is going to mean a lot of boilerplate for SVE,
|
||||
* which already has several variants of a lot of functions (*_z, *_m,
|
||||
* etc.), plus overloaded functions in C++ and generic selectors in C.
|
||||
*
|
||||
* Anyways, all this means that we're going to need to always define
|
||||
* the portable types.
|
||||
*
|
||||
* The good news is that at least we don't have to deal with
|
||||
* to/from_private functions; since the no-SVE versions will only be
|
||||
* called with non-SVE params. */
|
||||
|
||||
#if !defined(SIMDE_ARM_SVE_TYPES_H)
|
||||
#define SIMDE_ARM_SVE_TYPES_H
|
||||
|
||||
#include "../../simde-common.h"
|
||||
#include "../../simde-f16.h"
|
||||
|
||||
HEDLEY_DIAGNOSTIC_PUSH
|
||||
SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
|
||||
SIMDE_BEGIN_DECLS_
|
||||
|
||||
#if defined(SIMDE_VECTOR_SUBSCRIPT)
|
||||
#define SIMDE_ARM_SVE_DECLARE_VECTOR(Element_Type, Name, Vector_Size) Element_Type Name SIMDE_VECTOR(Vector_Size)
|
||||
#else
|
||||
#define SIMDE_ARM_SVE_DECLARE_VECTOR(Element_Type, Name, Vector_Size) Element_Type Name[(Vector_Size) / sizeof(Element_Type)]
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
typedef svbool_t simde_svbool_t;
|
||||
typedef svint8_t simde_svint8_t;
|
||||
typedef svint16_t simde_svint16_t;
|
||||
typedef svint32_t simde_svint32_t;
|
||||
typedef svint64_t simde_svint64_t;
|
||||
typedef svuint8_t simde_svuint8_t;
|
||||
typedef svuint16_t simde_svuint16_t;
|
||||
typedef svuint32_t simde_svuint32_t;
|
||||
typedef svuint64_t simde_svuint64_t;
|
||||
#if defined(__ARM_FEATURE_SVE_BF16)
|
||||
typedef svbfloat16_t simde_svbfloat16_t;
|
||||
#endif
|
||||
typedef svfloat16_t simde_svfloat16_t;
|
||||
typedef svfloat32_t simde_svfloat32_t;
|
||||
typedef svfloat64_t simde_svfloat64_t;
|
||||
typedef float32_t simde_float32_t;
|
||||
typedef float64_t simde_float64_t;
|
||||
#else
|
||||
#if SIMDE_NATURAL_VECTOR_SIZE > 0
|
||||
#define SIMDE_ARM_SVE_VECTOR_SIZE SIMDE_NATURAL_VECTOR_SIZE
|
||||
#else
|
||||
#define SIMDE_ARM_SVE_VECTOR_SIZE (128)
|
||||
#endif
|
||||
|
||||
typedef simde_float32 simde_float32_t;
|
||||
typedef simde_float64 simde_float64_t;
|
||||
|
||||
typedef union {
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(int8_t, values, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
__m512i m512i;
|
||||
#endif
|
||||
#if defined(SIMDE_X86_AVX2_NATIVE)
|
||||
__m256i m256i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m256i)];
|
||||
#endif
|
||||
#if defined(SIMDE_X86_SSE2_NATIVE)
|
||||
__m128i m128i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m128i)];
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
int8x16_t neon;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(signed char) altivec;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
v128_t v128;
|
||||
#endif
|
||||
} simde_svint8_t;
|
||||
|
||||
typedef union {
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(int16_t, values, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
__m512i m512i;
|
||||
#endif
|
||||
#if defined(SIMDE_X86_AVX2_NATIVE)
|
||||
__m256i m256i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m256i)];
|
||||
#endif
|
||||
#if defined(SIMDE_X86_SSE2_NATIVE)
|
||||
__m128i m128i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m128i)];
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
int16x8_t neon;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(signed short) altivec;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
v128_t v128;
|
||||
#endif
|
||||
} simde_svint16_t;
|
||||
|
||||
typedef union {
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(int32_t, values, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
__m512i m512i;
|
||||
#endif
|
||||
#if defined(SIMDE_X86_AVX2_NATIVE)
|
||||
__m256i m256i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m256i)];
|
||||
#endif
|
||||
#if defined(SIMDE_X86_SSE2_NATIVE)
|
||||
__m128i m128i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m128i)];
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
int32x4_t neon;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(signed int) altivec;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
v128_t v128;
|
||||
#endif
|
||||
} simde_svint32_t;
|
||||
|
||||
typedef union {
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(int64_t, values, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
__m512i m512i;
|
||||
#endif
|
||||
#if defined(SIMDE_X86_AVX2_NATIVE)
|
||||
__m256i m256i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m256i)];
|
||||
#endif
|
||||
#if defined(SIMDE_X86_SSE2_NATIVE)
|
||||
__m128i m128i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m128i)];
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
int64x2_t neon;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_POWER_ALTIVEC_P7_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(signed long long int) altivec;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
v128_t v128;
|
||||
#endif
|
||||
} simde_svint64_t;
|
||||
|
||||
typedef union {
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(uint8_t, values, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
__m512i m512i;
|
||||
#endif
|
||||
#if defined(SIMDE_X86_AVX2_NATIVE)
|
||||
__m256i m256i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m256i)];
|
||||
#endif
|
||||
#if defined(SIMDE_X86_SSE2_NATIVE)
|
||||
__m128i m128i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m128i)];
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
uint8x16_t neon;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(unsigned char) altivec;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
v128_t v128;
|
||||
#endif
|
||||
} simde_svuint8_t;
|
||||
|
||||
typedef union {
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(uint16_t, values, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
__m512i m512i;
|
||||
#endif
|
||||
#if defined(SIMDE_X86_AVX2_NATIVE)
|
||||
__m256i m256i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m256i)];
|
||||
#endif
|
||||
#if defined(SIMDE_X86_SSE2_NATIVE)
|
||||
__m128i m128i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m128i)];
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
uint16x8_t neon;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(unsigned short) altivec;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
v128_t v128;
|
||||
#endif
|
||||
} simde_svuint16_t;
|
||||
|
||||
typedef union {
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(uint32_t, values, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
__m512i m512i;
|
||||
#endif
|
||||
#if defined(SIMDE_X86_AVX2_NATIVE)
|
||||
__m256i m256i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m256i)];
|
||||
#endif
|
||||
#if defined(SIMDE_X86_SSE2_NATIVE)
|
||||
__m128i m128i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m128i)];
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
uint32x4_t neon;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(unsigned int) altivec;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
v128_t v128;
|
||||
#endif
|
||||
} simde_svuint32_t;
|
||||
|
||||
typedef union {
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(uint64_t, values, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
__m512i m512i;
|
||||
#endif
|
||||
#if defined(SIMDE_X86_AVX2_NATIVE)
|
||||
__m256i m256i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m256i)];
|
||||
#endif
|
||||
#if defined(SIMDE_X86_SSE2_NATIVE)
|
||||
__m128i m128i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m128i)];
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
uint64x2_t neon;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_POWER_ALTIVEC_P7_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(unsigned long long int) altivec;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
v128_t v128;
|
||||
#endif
|
||||
} simde_svuint64_t;
|
||||
|
||||
typedef union {
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(uint16_t, values, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
__m512i m512i;
|
||||
#endif
|
||||
#if defined(SIMDE_X86_AVX2_NATIVE)
|
||||
__m256i m256i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m256i)];
|
||||
#endif
|
||||
#if defined(SIMDE_X86_SSE2_NATIVE)
|
||||
__m128i m128i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m128i)];
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
|
||||
float16x8_t neon;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(unsigned short) altivec;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
v128_t v128;
|
||||
#endif
|
||||
} simde_svfloat16_t;
|
||||
|
||||
typedef union {
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(uint16_t, values, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
__m512i m512i;
|
||||
#endif
|
||||
#if defined(SIMDE_X86_AVX2_NATIVE)
|
||||
__m256i m256i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m256i)];
|
||||
#endif
|
||||
#if defined(SIMDE_X86_SSE2_NATIVE)
|
||||
__m128i m128i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m128i)];
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(unsigned short) altivec;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
v128_t v128;
|
||||
#endif
|
||||
} simde_svbfloat16_t;
|
||||
|
||||
typedef union {
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(simde_float32, values, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
__m512 m512;
|
||||
#endif
|
||||
#if defined(SIMDE_X86_AVX_NATIVE)
|
||||
__m256 m256[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m256)];
|
||||
#endif
|
||||
#if defined(SIMDE_X86_SSE_NATIVE)
|
||||
__m128 m128[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m128)];
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
float32x4_t neon;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(float) altivec;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
v128_t v128;
|
||||
#endif
|
||||
} simde_svfloat32_t;
|
||||
|
||||
typedef union {
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(simde_float64, values, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
__m512d m512d;
|
||||
#endif
|
||||
#if defined(SIMDE_X86_AVX2_NATIVE)
|
||||
__m256d m256d[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m256d)];
|
||||
#endif
|
||||
#if defined(SIMDE_X86_SSE2_NATIVE)
|
||||
__m128d m128d[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m128d)];
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
float64x2_t neon;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_POWER_ALTIVEC_P7_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(double) altivec;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
v128_t v128;
|
||||
#endif
|
||||
} simde_svfloat64_t;
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
typedef struct {
|
||||
__mmask64 value;
|
||||
int type;
|
||||
} simde_svbool_t;
|
||||
|
||||
#if defined(__BMI2__)
|
||||
static const uint64_t simde_arm_sve_mask_bp_lo_ = UINT64_C(0x5555555555555555);
|
||||
static const uint64_t simde_arm_sve_mask_bp_hi_ = UINT64_C(0xaaaaaaaaaaaaaaaa);
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask64
|
||||
simde_arm_sve_mmask32_to_mmask64(__mmask32 m) {
|
||||
return HEDLEY_STATIC_CAST(__mmask64,
|
||||
_pdep_u64(HEDLEY_STATIC_CAST(uint64_t, m), simde_arm_sve_mask_bp_lo_) |
|
||||
_pdep_u64(HEDLEY_STATIC_CAST(uint64_t, m), simde_arm_sve_mask_bp_hi_));
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask32
|
||||
simde_arm_sve_mmask16_to_mmask32(__mmask16 m) {
|
||||
return HEDLEY_STATIC_CAST(__mmask32,
|
||||
_pdep_u32(HEDLEY_STATIC_CAST(uint32_t, m), HEDLEY_STATIC_CAST(uint32_t, simde_arm_sve_mask_bp_lo_)) |
|
||||
_pdep_u32(HEDLEY_STATIC_CAST(uint32_t, m), HEDLEY_STATIC_CAST(uint32_t, simde_arm_sve_mask_bp_hi_)));
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask16
|
||||
simde_arm_sve_mmask8_to_mmask16(__mmask8 m) {
|
||||
return HEDLEY_STATIC_CAST(__mmask16,
|
||||
_pdep_u32(HEDLEY_STATIC_CAST(uint32_t, m), HEDLEY_STATIC_CAST(uint32_t, simde_arm_sve_mask_bp_lo_)) |
|
||||
_pdep_u32(HEDLEY_STATIC_CAST(uint32_t, m), HEDLEY_STATIC_CAST(uint32_t, simde_arm_sve_mask_bp_hi_)));
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask8
|
||||
simde_arm_sve_mmask4_to_mmask8(__mmask8 m) {
|
||||
return HEDLEY_STATIC_CAST(__mmask8,
|
||||
_pdep_u32(HEDLEY_STATIC_CAST(uint32_t, m), HEDLEY_STATIC_CAST(uint32_t, simde_arm_sve_mask_bp_lo_)) |
|
||||
_pdep_u32(HEDLEY_STATIC_CAST(uint32_t, m), HEDLEY_STATIC_CAST(uint32_t, simde_arm_sve_mask_bp_hi_)));
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask32
|
||||
simde_arm_sve_mmask64_to_mmask32(__mmask64 m) {
|
||||
return HEDLEY_STATIC_CAST(__mmask32,
|
||||
_pext_u64(HEDLEY_STATIC_CAST(uint64_t, m), HEDLEY_STATIC_CAST(uint64_t, simde_arm_sve_mask_bp_lo_)) &
|
||||
_pext_u64(HEDLEY_STATIC_CAST(uint64_t, m), HEDLEY_STATIC_CAST(uint64_t, simde_arm_sve_mask_bp_hi_)));
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask16
|
||||
simde_arm_sve_mmask32_to_mmask16(__mmask32 m) {
|
||||
return HEDLEY_STATIC_CAST(__mmask16,
|
||||
_pext_u32(HEDLEY_STATIC_CAST(uint32_t, m), HEDLEY_STATIC_CAST(uint32_t, simde_arm_sve_mask_bp_lo_)) &
|
||||
_pext_u32(HEDLEY_STATIC_CAST(uint32_t, m), HEDLEY_STATIC_CAST(uint32_t, simde_arm_sve_mask_bp_hi_)));
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask8
|
||||
simde_arm_sve_mmask16_to_mmask8(__mmask16 m) {
|
||||
return HEDLEY_STATIC_CAST(__mmask8,
|
||||
_pext_u32(HEDLEY_STATIC_CAST(uint32_t, m), HEDLEY_STATIC_CAST(uint32_t, simde_arm_sve_mask_bp_lo_)) &
|
||||
_pext_u32(HEDLEY_STATIC_CAST(uint32_t, m), HEDLEY_STATIC_CAST(uint32_t, simde_arm_sve_mask_bp_hi_)));
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask8
|
||||
simde_arm_sve_mmask8_to_mmask4(__mmask8 m) {
|
||||
return HEDLEY_STATIC_CAST(__mmask8,
|
||||
_pext_u32(HEDLEY_STATIC_CAST(uint32_t, m), HEDLEY_STATIC_CAST(uint32_t, simde_arm_sve_mask_bp_lo_)) &
|
||||
_pext_u32(HEDLEY_STATIC_CAST(uint32_t, m), HEDLEY_STATIC_CAST(uint32_t, simde_arm_sve_mask_bp_hi_)));
|
||||
}
|
||||
#else
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask64
|
||||
simde_arm_sve_mmask32_to_mmask64(__mmask32 m) {
|
||||
uint64_t e = HEDLEY_STATIC_CAST(uint64_t, m);
|
||||
uint64_t o = HEDLEY_STATIC_CAST(uint64_t, m);
|
||||
|
||||
e = (e | (e << 16)) & UINT64_C(0x0000ffff0000ffff);
|
||||
e = (e | (e << 8)) & UINT64_C(0x00ff00ff00ff00ff);
|
||||
e = (e | (e << 4)) & UINT64_C(0x0f0f0f0f0f0f0f0f);
|
||||
e = (e | (e << 2)) & UINT64_C(0x3333333333333333);
|
||||
e = (e | (e << 1)) & UINT64_C(0x5555555555555555);
|
||||
|
||||
o = (o | (o << 16)) & UINT64_C(0x0000ffff0000ffff);
|
||||
o = (o | (o << 8)) & UINT64_C(0x00ff00ff00ff00ff);
|
||||
o = (o | (o << 4)) & UINT64_C(0x0f0f0f0f0f0f0f0f);
|
||||
o = (o | (o << 2)) & UINT64_C(0x3333333333333333);
|
||||
o = (o | (o << 1)) & UINT64_C(0x5555555555555555);
|
||||
|
||||
return HEDLEY_STATIC_CAST(__mmask64, e | (o << 1));
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask32
|
||||
simde_arm_sve_mmask16_to_mmask32(__mmask16 m) {
|
||||
uint32_t e = HEDLEY_STATIC_CAST(uint32_t, m);
|
||||
uint32_t o = HEDLEY_STATIC_CAST(uint32_t, m);
|
||||
|
||||
e = (e | (e << 8)) & UINT32_C(0x00FF00FF);
|
||||
e = (e | (e << 4)) & UINT32_C(0x0F0F0F0F);
|
||||
e = (e | (e << 2)) & UINT32_C(0x33333333);
|
||||
e = (e | (e << 1)) & UINT32_C(0x55555555);
|
||||
|
||||
o = (o | (o << 8)) & UINT32_C(0x00FF00FF);
|
||||
o = (o | (o << 4)) & UINT32_C(0x0F0F0F0F);
|
||||
o = (o | (o << 2)) & UINT32_C(0x33333333);
|
||||
o = (o | (o << 1)) & UINT32_C(0x55555555);
|
||||
|
||||
return HEDLEY_STATIC_CAST(__mmask32, e | (o << 1));
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask16
|
||||
simde_arm_sve_mmask8_to_mmask16(__mmask8 m) {
|
||||
uint16_t e = HEDLEY_STATIC_CAST(uint16_t, m);
|
||||
uint16_t o = HEDLEY_STATIC_CAST(uint16_t, m);
|
||||
|
||||
e = (e | (e << 4)) & UINT16_C(0x0f0f);
|
||||
e = (e | (e << 2)) & UINT16_C(0x3333);
|
||||
e = (e | (e << 1)) & UINT16_C(0x5555);
|
||||
|
||||
o = (o | (o << 4)) & UINT16_C(0x0f0f);
|
||||
o = (o | (o << 2)) & UINT16_C(0x3333);
|
||||
o = (o | (o << 1)) & UINT16_C(0x5555);
|
||||
|
||||
return HEDLEY_STATIC_CAST(uint16_t, e | (o << 1));
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask8
|
||||
simde_arm_sve_mmask4_to_mmask8(__mmask8 m) {
|
||||
uint8_t e = HEDLEY_STATIC_CAST(uint8_t, m);
|
||||
uint8_t o = HEDLEY_STATIC_CAST(uint8_t, m);
|
||||
|
||||
e = (e | (e << 2)) & UINT8_C(0x33);
|
||||
e = (e | (e << 1)) & UINT8_C(0x55);
|
||||
|
||||
o = (o | (o << 2)) & UINT8_C(0x33);
|
||||
o = (o | (o << 1)) & UINT8_C(0x55);
|
||||
|
||||
return HEDLEY_STATIC_CAST(uint8_t, e | (o << 1));
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask32
|
||||
simde_arm_sve_mmask64_to_mmask32(__mmask64 m) {
|
||||
uint64_t l = (HEDLEY_STATIC_CAST(uint64_t, m) ) & UINT64_C(0x5555555555555555);
|
||||
l = (l | (l >> 1)) & UINT64_C(0x3333333333333333);
|
||||
l = (l | (l >> 2)) & UINT64_C(0x0f0f0f0f0f0f0f0f);
|
||||
l = (l | (l >> 4)) & UINT64_C(0x00ff00ff00ff00ff);
|
||||
l = (l | (l >> 8)) & UINT64_C(0x0000ffff0000ffff);
|
||||
|
||||
uint64_t h = (HEDLEY_STATIC_CAST(uint64_t, m) >> 1) & UINT64_C(0x5555555555555555);
|
||||
h = (h | (h >> 1)) & UINT64_C(0x3333333333333333);
|
||||
h = (h | (h >> 2)) & UINT64_C(0x0f0f0f0f0f0f0f0f);
|
||||
h = (h | (h >> 4)) & UINT64_C(0x00ff00ff00ff00ff);
|
||||
h = (h | (h >> 8)) & UINT64_C(0x0000ffff0000ffff);
|
||||
|
||||
return HEDLEY_STATIC_CAST(uint32_t, l & h);
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask16
|
||||
simde_arm_sve_mmask32_to_mmask16(__mmask32 m) {
|
||||
uint32_t l = (HEDLEY_STATIC_CAST(uint32_t, m) ) & UINT32_C(0x55555555);
|
||||
l = (l | (l >> 1)) & UINT32_C(0x33333333);
|
||||
l = (l | (l >> 2)) & UINT32_C(0x0f0f0f0f);
|
||||
l = (l | (l >> 4)) & UINT32_C(0x00ff00ff);
|
||||
l = (l | (l >> 8)) & UINT32_C(0x0000ffff);
|
||||
|
||||
uint32_t h = (HEDLEY_STATIC_CAST(uint32_t, m) >> 1) & UINT32_C(0x55555555);
|
||||
h = (h | (h >> 1)) & UINT32_C(0x33333333);
|
||||
h = (h | (h >> 2)) & UINT32_C(0x0f0f0f0f);
|
||||
h = (h | (h >> 4)) & UINT32_C(0x00ff00ff);
|
||||
h = (h | (h >> 8)) & UINT32_C(0x0000ffff);
|
||||
|
||||
return HEDLEY_STATIC_CAST(uint16_t, l & h);
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask8
|
||||
simde_arm_sve_mmask16_to_mmask8(__mmask16 m) {
|
||||
uint16_t l = (HEDLEY_STATIC_CAST(uint16_t, m) ) & UINT16_C(0x5555);
|
||||
l = (l | (l >> 1)) & UINT16_C(0x3333);
|
||||
l = (l | (l >> 2)) & UINT16_C(0x0f0f);
|
||||
l = (l | (l >> 4)) & UINT16_C(0x00ff);
|
||||
|
||||
uint16_t h = (HEDLEY_STATIC_CAST(uint16_t, m) >> 1) & UINT16_C(0x5555);
|
||||
h = (h | (h >> 1)) & UINT16_C(0x3333);
|
||||
h = (h | (h >> 2)) & UINT16_C(0x0f0f);
|
||||
h = (h | (h >> 4)) & UINT16_C(0x00ff);
|
||||
|
||||
return HEDLEY_STATIC_CAST(uint8_t, l & h);
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
__mmask8
|
||||
simde_arm_sve_mmask8_to_mmask4(__mmask8 m) {
|
||||
uint8_t l = (HEDLEY_STATIC_CAST(uint8_t, m) ) & UINT8_C(0x55);
|
||||
l = (l | (l >> 1)) & UINT8_C(0x33);
|
||||
l = (l | (l >> 2)) & UINT8_C(0x0f);
|
||||
l = (l | (l >> 4)) & UINT8_C(0xff);
|
||||
|
||||
uint8_t h = (HEDLEY_STATIC_CAST(uint8_t, m) >> 1) & UINT8_C(0x55);
|
||||
h = (h | (h >> 1)) & UINT8_C(0x33);
|
||||
h = (h | (h >> 2)) & UINT8_C(0x0f);
|
||||
h = (h | (h >> 4)) & UINT8_C(0xff);
|
||||
|
||||
return HEDLEY_STATIC_CAST(uint8_t, l & h);
|
||||
}
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK64,
|
||||
SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK32,
|
||||
SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK16,
|
||||
SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK8,
|
||||
#if SIMDE_ARM_SVE_VECTOR_SIZE < 512
|
||||
SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK4,
|
||||
#endif
|
||||
} simde_svbool_mmask_type;
|
||||
|
||||
HEDLEY_CONST HEDLEY_ALWAYS_INLINE
|
||||
simde_svbool_t
|
||||
simde_svbool_from_mmask64(__mmask64 mi) {
|
||||
simde_svbool_t b;
|
||||
|
||||
b.value = HEDLEY_STATIC_CAST(__mmask64, mi);
|
||||
b.type = SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK64;
|
||||
|
||||
return b;
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES HEDLEY_CONST
|
||||
simde_svbool_t
|
||||
simde_svbool_from_mmask32(__mmask32 mi) {
|
||||
simde_svbool_t b;
|
||||
|
||||
b.value = HEDLEY_STATIC_CAST(__mmask64, mi);
|
||||
b.type = SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK32;
|
||||
|
||||
return b;
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES HEDLEY_CONST
|
||||
simde_svbool_t
|
||||
simde_svbool_from_mmask16(__mmask16 mi) {
|
||||
simde_svbool_t b;
|
||||
|
||||
b.value = HEDLEY_STATIC_CAST(__mmask64, mi);
|
||||
b.type = SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK16;
|
||||
|
||||
return b;
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES HEDLEY_CONST
|
||||
simde_svbool_t
|
||||
simde_svbool_from_mmask8(__mmask8 mi) {
|
||||
simde_svbool_t b;
|
||||
|
||||
b.value = HEDLEY_STATIC_CAST(__mmask64, mi);
|
||||
b.type = SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK8;
|
||||
|
||||
return b;
|
||||
}
|
||||
|
||||
#if SIMDE_ARM_SVE_VECTOR_SIZE < 512
|
||||
SIMDE_FUNCTION_ATTRIBUTES HEDLEY_CONST
|
||||
simde_svbool_t
|
||||
simde_svbool_from_mmask4(__mmask8 mi) {
|
||||
simde_svbool_t b;
|
||||
|
||||
b.value = HEDLEY_STATIC_CAST(__mmask64, mi);
|
||||
b.type = SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK4;
|
||||
|
||||
return b;
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES HEDLEY_CONST
|
||||
__mmask8
|
||||
simde_svbool_to_mmask4(simde_svbool_t b) {
|
||||
__mmask64 tmp = b.value;
|
||||
|
||||
switch (b.type) {
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK64:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask64_to_mmask32(HEDLEY_STATIC_CAST(__mmask64, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK32:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask32_to_mmask16(HEDLEY_STATIC_CAST(__mmask32, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK16:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask16_to_mmask8(HEDLEY_STATIC_CAST(__mmask16, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK8:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask8_to_mmask4(HEDLEY_STATIC_CAST(__mmask8, tmp)));
|
||||
}
|
||||
|
||||
return HEDLEY_STATIC_CAST(__mmask8, tmp);
|
||||
}
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES HEDLEY_CONST
|
||||
__mmask8
|
||||
simde_svbool_to_mmask8(simde_svbool_t b) {
|
||||
__mmask64 tmp = b.value;
|
||||
|
||||
switch (b.type) {
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK64:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask64_to_mmask32(HEDLEY_STATIC_CAST(__mmask64, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK32:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask32_to_mmask16(HEDLEY_STATIC_CAST(__mmask32, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK16:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask16_to_mmask8(HEDLEY_STATIC_CAST(__mmask16, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK8:
|
||||
break;
|
||||
|
||||
#if SIMDE_ARM_SVE_VECTOR_SIZE < 512
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK4:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask4_to_mmask8(HEDLEY_STATIC_CAST(__mmask8, tmp)));
|
||||
#endif
|
||||
}
|
||||
|
||||
return HEDLEY_STATIC_CAST(__mmask8, tmp);
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES HEDLEY_CONST
|
||||
__mmask16
|
||||
simde_svbool_to_mmask16(simde_svbool_t b) {
|
||||
__mmask64 tmp = b.value;
|
||||
|
||||
switch (b.type) {
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK64:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask64_to_mmask32(HEDLEY_STATIC_CAST(__mmask64, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK32:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask32_to_mmask16(HEDLEY_STATIC_CAST(__mmask32, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK16:
|
||||
break;
|
||||
|
||||
#if SIMDE_ARM_SVE_VECTOR_SIZE < 512
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK4:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask4_to_mmask8(HEDLEY_STATIC_CAST(__mmask8, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
#endif
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK8:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask8_to_mmask16(HEDLEY_STATIC_CAST(__mmask8, tmp)));
|
||||
}
|
||||
|
||||
return HEDLEY_STATIC_CAST(__mmask16, tmp);
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES HEDLEY_CONST
|
||||
__mmask32
|
||||
simde_svbool_to_mmask32(simde_svbool_t b) {
|
||||
__mmask64 tmp = b.value;
|
||||
|
||||
switch (b.type) {
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK64:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask64_to_mmask32(HEDLEY_STATIC_CAST(__mmask64, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK32:
|
||||
break;
|
||||
|
||||
#if SIMDE_ARM_SVE_VECTOR_SIZE < 512
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK4:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask4_to_mmask8(HEDLEY_STATIC_CAST(__mmask8, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
#endif
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK8:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask8_to_mmask16(HEDLEY_STATIC_CAST(__mmask8, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK16:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask16_to_mmask32(HEDLEY_STATIC_CAST(__mmask16, tmp)));
|
||||
}
|
||||
|
||||
return HEDLEY_STATIC_CAST(__mmask32, tmp);
|
||||
}
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES HEDLEY_CONST
|
||||
__mmask64
|
||||
simde_svbool_to_mmask64(simde_svbool_t b) {
|
||||
__mmask64 tmp = b.value;
|
||||
|
||||
switch (b.type) {
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK64:
|
||||
break;
|
||||
|
||||
#if SIMDE_ARM_SVE_VECTOR_SIZE < 512
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK4:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask4_to_mmask8(HEDLEY_STATIC_CAST(__mmask8, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
#endif
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK8:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask8_to_mmask16(HEDLEY_STATIC_CAST(__mmask8, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK16:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask16_to_mmask32(HEDLEY_STATIC_CAST(__mmask16, tmp)));
|
||||
HEDLEY_FALL_THROUGH;
|
||||
case SIMDE_ARM_SVE_SVBOOL_TYPE_MMASK32:
|
||||
tmp = HEDLEY_STATIC_CAST(__mmask64, simde_arm_sve_mmask32_to_mmask64(HEDLEY_STATIC_CAST(__mmask32, tmp)));
|
||||
}
|
||||
|
||||
return HEDLEY_STATIC_CAST(__mmask64, tmp);
|
||||
}
|
||||
|
||||
/* TODO: we're going to need need svbool_to/from_svint* functions
|
||||
* for when we can't implement a function using AVX-512. */
|
||||
#else
|
||||
typedef union {
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR( int8_t, values_i8, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR( int16_t, values_i16, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR( int32_t, values_i32, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR( int64_t, values_i64, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR( uint8_t, values_u8, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(uint16_t, values_u16, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(uint32_t, values_u32, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
SIMDE_ARM_SVE_DECLARE_VECTOR(uint64_t, values_u64, (SIMDE_ARM_SVE_VECTOR_SIZE / 8));
|
||||
|
||||
#if defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512)
|
||||
__m512i m512i;
|
||||
#endif
|
||||
#if defined(SIMDE_X86_AVX2_NATIVE)
|
||||
__m256i m256i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m256i)];
|
||||
#endif
|
||||
#if defined(SIMDE_X86_SSE2_NATIVE)
|
||||
__m128i m128i[(SIMDE_ARM_SVE_VECTOR_SIZE / 8) / sizeof(__m128i)];
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
int8x16_t neon_i8;
|
||||
int16x8_t neon_i16;
|
||||
int32x4_t neon_i32;
|
||||
int64x2_t neon_i64;
|
||||
uint8x16_t neon_u8;
|
||||
uint16x8_t neon_u16;
|
||||
uint32x4_t neon_u32;
|
||||
uint64x2_t neon_u64;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(SIMDE_POWER_ALTIVEC_BOOL char) altivec_b8;
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(SIMDE_POWER_ALTIVEC_BOOL short) altivec_b16;
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(SIMDE_POWER_ALTIVEC_BOOL int) altivec_b32;
|
||||
#endif
|
||||
#if defined(SIMDE_POWER_ALTIVEC_P7_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
|
||||
SIMDE_POWER_ALTIVEC_VECTOR(SIMDE_POWER_ALTIVEC_BOOL long long) altivec_b64;
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_WASM_SIMD128_NATIVE)
|
||||
v128_t v128;
|
||||
#endif
|
||||
} simde_svbool_t;
|
||||
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svbool_to_svint8, simde_svint8_t, simde_svbool_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svbool_from_svint8, simde_svbool_t, simde_svint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svbool_to_svint16, simde_svint16_t, simde_svbool_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_(simde_svbool_from_svint16, simde_svbool_t, simde_svint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svbool_to_svint32, simde_svint32_t, simde_svbool_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_(simde_svbool_from_svint32, simde_svbool_t, simde_svint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svbool_to_svint64, simde_svint64_t, simde_svbool_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_(simde_svbool_from_svint64, simde_svbool_t, simde_svint64_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svbool_to_svuint8, simde_svuint8_t, simde_svbool_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_(simde_svbool_from_svuint8, simde_svbool_t, simde_svuint8_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svbool_to_svuint16, simde_svuint16_t, simde_svbool_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_(simde_svbool_from_svuint16, simde_svbool_t, simde_svuint16_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svbool_to_svuint32, simde_svuint32_t, simde_svbool_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_(simde_svbool_from_svuint32, simde_svbool_t, simde_svuint32_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_( simde_svbool_to_svuint64, simde_svuint64_t, simde_svbool_t)
|
||||
SIMDE_DEFINE_CONVERSION_FUNCTION_(simde_svbool_from_svuint64, simde_svbool_t, simde_svuint64_t)
|
||||
#endif
|
||||
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
typedef simde_svbool_t svbool_t;
|
||||
typedef simde_svint8_t svint8_t;
|
||||
typedef simde_svint16_t svint16_t;
|
||||
typedef simde_svint32_t svint32_t;
|
||||
typedef simde_svint64_t svint64_t;
|
||||
typedef simde_svuint8_t svuint8_t;
|
||||
typedef simde_svuint16_t svuint16_t;
|
||||
typedef simde_svuint32_t svuint32_t;
|
||||
typedef simde_svuint64_t svuint64_t;
|
||||
typedef simde_svfloat16_t svfloat16_t;
|
||||
typedef simde_svbfloat16_t svbfloat16_t;
|
||||
typedef simde_svfloat32_t svfloat32_t;
|
||||
typedef simde_svfloat64_t svfloat64_t;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if !defined(SIMDE_ARM_SVE_DEFAULT_UNDEFINED_SUFFIX)
|
||||
#define SIMDE_ARM_SVE_DEFAULT_UNDEFINED_SUFFIX z
|
||||
#endif
|
||||
#define SIMDE_ARM_SVE_UNDEFINED_SYMBOL(name) HEDLEY_CONCAT3(name, _, SIMDE_ARM_SVE_DEFAULT_UNDEFINED_SUFFIX)
|
||||
|
||||
SIMDE_END_DECLS_
|
||||
HEDLEY_DIAGNOSTIC_POP
|
||||
|
||||
/* These are going to be used pretty much everywhere since they are
|
||||
* used to create the loops SVE requires. Since we want to support
|
||||
* only including the files you need instead of just using sve.h,
|
||||
* it's helpful to pull these in here. While this file is called
|
||||
* arm/sve/types.h, it might be better to think of it more as
|
||||
* arm/sve/common.h. */
|
||||
#include "cnt.h"
|
||||
#include "ld1.h"
|
||||
#include "ptest.h"
|
||||
#include "ptrue.h"
|
||||
#include "st1.h"
|
||||
#include "whilelt.h"
|
||||
|
||||
#endif /* SIMDE_ARM_SVE_TYPES_H */
|
||||
@@ -0,0 +1,843 @@
|
||||
/* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use, copy,
|
||||
* modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
* of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Copyright:
|
||||
* 2021 Evan Nemerson <evan@nemerson.com>
|
||||
*/
|
||||
|
||||
#if !defined(SIMDE_ARM_SVE_WHILELT_H)
|
||||
#define SIMDE_ARM_SVE_WHILELT_H
|
||||
|
||||
#include "types.h"
|
||||
|
||||
HEDLEY_DIAGNOSTIC_PUSH
|
||||
SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b8_s32(int32_t op1, int32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b8_s32(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask64(HEDLEY_STATIC_CAST(__mmask64, 0));
|
||||
|
||||
int_fast32_t remaining = (HEDLEY_STATIC_CAST(int_fast32_t, op2) - HEDLEY_STATIC_CAST(int_fast32_t, op1));
|
||||
__mmask64 r = ~HEDLEY_STATIC_CAST(__mmask64, 0);
|
||||
if (HEDLEY_UNLIKELY(remaining < 64)) {
|
||||
r >>= 64 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask64(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask32(HEDLEY_STATIC_CAST(__mmask32, 0));
|
||||
|
||||
int_fast32_t remaining = (HEDLEY_STATIC_CAST(int_fast32_t, op2) - HEDLEY_STATIC_CAST(int_fast32_t, op1));
|
||||
__mmask32 r = HEDLEY_STATIC_CAST(__mmask32, ~UINT32_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 32)) {
|
||||
r >>= 32 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask32(r);
|
||||
#else
|
||||
simde_svint8_t r;
|
||||
|
||||
int_fast32_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(int_fast32_t, op2) - HEDLEY_STATIC_CAST(int_fast32_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntb()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~UINT8_C(0) : UINT8_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint8(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b8_s32
|
||||
#define svwhilelt_b8_s32(op1, op2) simde_svwhilelt_b8_s32(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b16_s32(int32_t op1, int32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b16_s32(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask32(HEDLEY_STATIC_CAST(__mmask32, 0));
|
||||
|
||||
int_fast32_t remaining = (HEDLEY_STATIC_CAST(int_fast32_t, op2) - HEDLEY_STATIC_CAST(int_fast32_t, op1));
|
||||
__mmask32 r = HEDLEY_STATIC_CAST(__mmask32, ~UINT32_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 32)) {
|
||||
r >>= 32 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask32(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask16(HEDLEY_STATIC_CAST(__mmask16, 0));
|
||||
|
||||
int_fast32_t remaining = (HEDLEY_STATIC_CAST(int_fast32_t, op2) - HEDLEY_STATIC_CAST(int_fast32_t, op1));
|
||||
__mmask16 r = HEDLEY_STATIC_CAST(__mmask16, ~UINT16_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 16)) {
|
||||
r >>= 16 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask16(r);
|
||||
#else
|
||||
simde_svint16_t r;
|
||||
|
||||
int_fast32_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(int_fast32_t, op2) - HEDLEY_STATIC_CAST(int_fast32_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcnth()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~UINT16_C(0) : UINT16_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint16(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b16_s32
|
||||
#define svwhilelt_b16_s32(op1, op2) simde_svwhilelt_b16_s32(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b32_s32(int32_t op1, int32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b32_s32(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask16(HEDLEY_STATIC_CAST(__mmask16, 0));
|
||||
|
||||
int_fast32_t remaining = (HEDLEY_STATIC_CAST(int_fast32_t, op2) - HEDLEY_STATIC_CAST(int_fast32_t, op1));
|
||||
__mmask16 r = HEDLEY_STATIC_CAST(__mmask16, ~UINT16_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 16)) {
|
||||
r >>= 16 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask16(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask8(HEDLEY_STATIC_CAST(__mmask8, 0));
|
||||
|
||||
int_fast32_t remaining = (HEDLEY_STATIC_CAST(int_fast32_t, op2) - HEDLEY_STATIC_CAST(int_fast32_t, op1));
|
||||
__mmask8 r = HEDLEY_STATIC_CAST(__mmask8, ~UINT8_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 8)) {
|
||||
r >>= 8 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask8(r);
|
||||
#else
|
||||
simde_svint32_t r;
|
||||
|
||||
int_fast32_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(int_fast32_t, op2) - HEDLEY_STATIC_CAST(int_fast32_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntw()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~INT32_C(0) : INT32_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint32(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b32_s32
|
||||
#define svwhilelt_b32_s32(op1, op2) simde_svwhilelt_b32_s32(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b64_s32(int32_t op1, int32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b64_s32(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask8(HEDLEY_STATIC_CAST(__mmask8, 0));
|
||||
|
||||
int_fast32_t remaining = (HEDLEY_STATIC_CAST(int_fast32_t, op2) - HEDLEY_STATIC_CAST(int_fast32_t, op1));
|
||||
__mmask8 r = HEDLEY_STATIC_CAST(__mmask8, ~UINT8_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 8)) {
|
||||
r >>= 8 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask8(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask4(HEDLEY_STATIC_CAST(__mmask8, 0));
|
||||
|
||||
int_fast32_t remaining = (HEDLEY_STATIC_CAST(int_fast32_t, op2) - HEDLEY_STATIC_CAST(int_fast32_t, op1));
|
||||
__mmask8 r = HEDLEY_STATIC_CAST(__mmask8, 0x0f);
|
||||
if (HEDLEY_UNLIKELY(remaining < 4)) {
|
||||
r >>= 4 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask4(r);
|
||||
#else
|
||||
simde_svint64_t r;
|
||||
|
||||
int_fast32_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(int_fast32_t, op2) - HEDLEY_STATIC_CAST(int_fast32_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntd()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~INT64_C(0) : INT64_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint64(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b64_s32
|
||||
#define svwhilelt_b64_s32(op1, op2) simde_svwhilelt_b64_s32(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b8_s64(int64_t op1, int64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b8_s64(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask64(HEDLEY_STATIC_CAST(__mmask64, 0));
|
||||
|
||||
int_fast64_t remaining = (HEDLEY_STATIC_CAST(int_fast64_t, op2) - HEDLEY_STATIC_CAST(int_fast64_t, op1));
|
||||
__mmask64 r = ~HEDLEY_STATIC_CAST(__mmask64, 0);
|
||||
if (HEDLEY_UNLIKELY(remaining < 64)) {
|
||||
r >>= 64 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask64(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask32(HEDLEY_STATIC_CAST(__mmask32, 0));
|
||||
|
||||
int_fast64_t remaining = (HEDLEY_STATIC_CAST(int_fast64_t, op2) - HEDLEY_STATIC_CAST(int_fast64_t, op1));
|
||||
__mmask32 r = HEDLEY_STATIC_CAST(__mmask32, ~UINT32_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 32)) {
|
||||
r >>= 32 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask32(r);
|
||||
#else
|
||||
simde_svint8_t r;
|
||||
|
||||
int_fast64_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(int_fast64_t, op2) - HEDLEY_STATIC_CAST(int_fast64_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntb()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~UINT8_C(0) : UINT8_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint8(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b8_s64
|
||||
#define svwhilelt_b8_s64(op1, op2) simde_svwhilelt_b8_s64(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b16_s64(int64_t op1, int64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b16_s64(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask32(HEDLEY_STATIC_CAST(__mmask32, 0));
|
||||
|
||||
int_fast64_t remaining = (HEDLEY_STATIC_CAST(int_fast64_t, op2) - HEDLEY_STATIC_CAST(int_fast64_t, op1));
|
||||
__mmask32 r = HEDLEY_STATIC_CAST(__mmask32, ~UINT32_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 32)) {
|
||||
r >>= 32 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask32(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask16(HEDLEY_STATIC_CAST(__mmask16, 0));
|
||||
|
||||
int_fast64_t remaining = (HEDLEY_STATIC_CAST(int_fast64_t, op2) - HEDLEY_STATIC_CAST(int_fast64_t, op1));
|
||||
__mmask16 r = HEDLEY_STATIC_CAST(__mmask16, ~UINT16_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 16)) {
|
||||
r >>= 16 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask16(r);
|
||||
#else
|
||||
simde_svint16_t r;
|
||||
|
||||
int_fast64_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(int_fast64_t, op2) - HEDLEY_STATIC_CAST(int_fast64_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcnth()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~UINT16_C(0) : UINT16_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint16(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b16_s64
|
||||
#define svwhilelt_b16_s64(op1, op2) simde_svwhilelt_b16_s64(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b32_s64(int64_t op1, int64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b32_s64(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask16(HEDLEY_STATIC_CAST(__mmask16, 0));
|
||||
|
||||
int_fast64_t remaining = (HEDLEY_STATIC_CAST(int_fast64_t, op2) - HEDLEY_STATIC_CAST(int_fast64_t, op1));
|
||||
__mmask16 r = HEDLEY_STATIC_CAST(__mmask16, ~UINT16_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 16)) {
|
||||
r >>= 16 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask16(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask8(HEDLEY_STATIC_CAST(__mmask8, 0));
|
||||
|
||||
int_fast64_t remaining = (HEDLEY_STATIC_CAST(int_fast64_t, op2) - HEDLEY_STATIC_CAST(int_fast64_t, op1));
|
||||
__mmask8 r = HEDLEY_STATIC_CAST(__mmask8, ~UINT8_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 8)) {
|
||||
r >>= 8 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask8(r);
|
||||
#else
|
||||
simde_svint64_t r;
|
||||
|
||||
int_fast64_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(int_fast64_t, op2) - HEDLEY_STATIC_CAST(int_fast64_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntw()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~INT64_C(0) : INT64_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint64(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b32_s64
|
||||
#define svwhilelt_b32_s64(op1, op2) simde_svwhilelt_b32_s64(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b64_s64(int64_t op1, int64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b64_s64(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask8(HEDLEY_STATIC_CAST(__mmask8, 0));
|
||||
|
||||
int_fast64_t remaining = (HEDLEY_STATIC_CAST(int_fast64_t, op2) - HEDLEY_STATIC_CAST(int_fast64_t, op1));
|
||||
__mmask8 r = HEDLEY_STATIC_CAST(__mmask8, ~UINT8_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 8)) {
|
||||
r >>= 8 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask8(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask4(HEDLEY_STATIC_CAST(__mmask8, 0));
|
||||
|
||||
int_fast64_t remaining = (HEDLEY_STATIC_CAST(int_fast64_t, op2) - HEDLEY_STATIC_CAST(int_fast64_t, op1));
|
||||
__mmask8 r = HEDLEY_STATIC_CAST(__mmask8, 0x0f);
|
||||
if (HEDLEY_UNLIKELY(remaining < 4)) {
|
||||
r >>= 4 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask4(r);
|
||||
#else
|
||||
simde_svint64_t r;
|
||||
|
||||
int_fast64_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(int_fast64_t, op2) - HEDLEY_STATIC_CAST(int_fast64_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntd()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~INT64_C(0) : INT64_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint64(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b64_s64
|
||||
#define svwhilelt_b64_s64(op1, op2) simde_svwhilelt_b64_s64(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b8_u32(uint32_t op1, uint32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b8_u32(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask64(HEDLEY_STATIC_CAST(__mmask64, 0));
|
||||
|
||||
uint_fast32_t remaining = (HEDLEY_STATIC_CAST(uint_fast32_t, op2) - HEDLEY_STATIC_CAST(uint_fast32_t, op1));
|
||||
__mmask64 r = ~HEDLEY_STATIC_CAST(__mmask64, 0);
|
||||
if (HEDLEY_UNLIKELY(remaining < 64)) {
|
||||
r >>= 64 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask64(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask32(HEDLEY_STATIC_CAST(__mmask32, 0));
|
||||
|
||||
uint_fast32_t remaining = (HEDLEY_STATIC_CAST(uint_fast32_t, op2) - HEDLEY_STATIC_CAST(uint_fast32_t, op1));
|
||||
__mmask32 r = HEDLEY_STATIC_CAST(__mmask32, ~UINT32_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 32)) {
|
||||
r >>= 32 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask32(r);
|
||||
#else
|
||||
simde_svint8_t r;
|
||||
|
||||
uint_fast32_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(uint_fast32_t, op2) - HEDLEY_STATIC_CAST(uint_fast32_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntb()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~UINT8_C(0) : UINT8_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint8(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b8_u32
|
||||
#define svwhilelt_b8_u32(op1, op2) simde_svwhilelt_b8_u32(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b16_u32(uint32_t op1, uint32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b16_u32(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask32(HEDLEY_STATIC_CAST(__mmask32, 0));
|
||||
|
||||
uint_fast32_t remaining = (HEDLEY_STATIC_CAST(uint_fast32_t, op2) - HEDLEY_STATIC_CAST(uint_fast32_t, op1));
|
||||
__mmask32 r = HEDLEY_STATIC_CAST(__mmask32, ~UINT32_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 32)) {
|
||||
r >>= 32 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask32(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask16(HEDLEY_STATIC_CAST(__mmask16, 0));
|
||||
|
||||
uint_fast32_t remaining = (HEDLEY_STATIC_CAST(uint_fast32_t, op2) - HEDLEY_STATIC_CAST(uint_fast32_t, op1));
|
||||
__mmask16 r = HEDLEY_STATIC_CAST(__mmask16, ~UINT16_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 16)) {
|
||||
r >>= 16 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask16(r);
|
||||
#else
|
||||
simde_svint16_t r;
|
||||
|
||||
uint_fast32_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(uint_fast32_t, op2) - HEDLEY_STATIC_CAST(uint_fast32_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcnth()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~UINT16_C(0) : UINT16_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint16(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b16_u32
|
||||
#define svwhilelt_b16_u32(op1, op2) simde_svwhilelt_b16_u32(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b32_u32(uint32_t op1, uint32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b32_u32(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask16(HEDLEY_STATIC_CAST(__mmask16, 0));
|
||||
|
||||
uint_fast32_t remaining = (HEDLEY_STATIC_CAST(uint_fast32_t, op2) - HEDLEY_STATIC_CAST(uint_fast32_t, op1));
|
||||
__mmask16 r = HEDLEY_STATIC_CAST(__mmask16, ~UINT16_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 16)) {
|
||||
r >>= 16 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask16(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask8(HEDLEY_STATIC_CAST(__mmask8, 0));
|
||||
|
||||
uint_fast32_t remaining = (HEDLEY_STATIC_CAST(uint_fast32_t, op2) - HEDLEY_STATIC_CAST(uint_fast32_t, op1));
|
||||
__mmask8 r = HEDLEY_STATIC_CAST(__mmask8, ~UINT8_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 8)) {
|
||||
r >>= 8 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask8(r);
|
||||
#else
|
||||
simde_svuint32_t r;
|
||||
|
||||
uint_fast32_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(uint_fast32_t, op2) - HEDLEY_STATIC_CAST(uint_fast32_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntw()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~UINT32_C(0) : UINT32_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svuint32(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b32_u32
|
||||
#define svwhilelt_b32_u32(op1, op2) simde_svwhilelt_b32_u32(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b64_u32(uint32_t op1, uint32_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b64_u32(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask8(HEDLEY_STATIC_CAST(__mmask8, 0));
|
||||
|
||||
uint_fast32_t remaining = (HEDLEY_STATIC_CAST(uint_fast32_t, op2) - HEDLEY_STATIC_CAST(uint_fast32_t, op1));
|
||||
__mmask8 r = HEDLEY_STATIC_CAST(__mmask8, ~UINT8_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 8)) {
|
||||
r >>= 8 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask8(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask4(HEDLEY_STATIC_CAST(__mmask8, 0));
|
||||
|
||||
uint_fast32_t remaining = (HEDLEY_STATIC_CAST(uint_fast32_t, op2) - HEDLEY_STATIC_CAST(uint_fast32_t, op1));
|
||||
__mmask8 r = HEDLEY_STATIC_CAST(__mmask8, 0x0f);
|
||||
if (HEDLEY_UNLIKELY(remaining < 4)) {
|
||||
r >>= 4 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask4(r);
|
||||
#else
|
||||
simde_svint64_t r;
|
||||
|
||||
uint_fast32_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(uint_fast32_t, op2) - HEDLEY_STATIC_CAST(uint_fast32_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntd()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~INT64_C(0) : INT64_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint64(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b64_u32
|
||||
#define svwhilelt_b64_u32(op1, op2) simde_svwhilelt_b64_u32(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b8_u64(uint64_t op1, uint64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b8_u64(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask64(HEDLEY_STATIC_CAST(__mmask64, 0));
|
||||
|
||||
uint_fast64_t remaining = (HEDLEY_STATIC_CAST(uint_fast64_t, op2) - HEDLEY_STATIC_CAST(uint_fast64_t, op1));
|
||||
__mmask64 r = ~HEDLEY_STATIC_CAST(__mmask64, 0);
|
||||
if (HEDLEY_UNLIKELY(remaining < 64)) {
|
||||
r >>= 64 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask64(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask32(HEDLEY_STATIC_CAST(__mmask32, 0));
|
||||
|
||||
uint_fast64_t remaining = (HEDLEY_STATIC_CAST(uint_fast64_t, op2) - HEDLEY_STATIC_CAST(uint_fast64_t, op1));
|
||||
__mmask32 r = HEDLEY_STATIC_CAST(__mmask32, ~UINT64_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 32)) {
|
||||
r >>= 32 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask32(r);
|
||||
#else
|
||||
simde_svint8_t r;
|
||||
|
||||
uint_fast64_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(uint_fast64_t, op2) - HEDLEY_STATIC_CAST(uint_fast64_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntb()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~UINT8_C(0) : UINT8_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint8(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b8_u64
|
||||
#define svwhilelt_b8_u64(op1, op2) simde_svwhilelt_b8_u64(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b16_u64(uint64_t op1, uint64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b16_u64(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask32(HEDLEY_STATIC_CAST(__mmask32, 0));
|
||||
|
||||
uint_fast64_t remaining = (HEDLEY_STATIC_CAST(uint_fast64_t, op2) - HEDLEY_STATIC_CAST(uint_fast64_t, op1));
|
||||
__mmask32 r = HEDLEY_STATIC_CAST(__mmask32, ~UINT32_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 32)) {
|
||||
r >>= 32 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask32(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask16(HEDLEY_STATIC_CAST(__mmask16, 0));
|
||||
|
||||
uint_fast64_t remaining = (HEDLEY_STATIC_CAST(uint_fast64_t, op2) - HEDLEY_STATIC_CAST(uint_fast64_t, op1));
|
||||
__mmask16 r = HEDLEY_STATIC_CAST(__mmask16, ~UINT16_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 16)) {
|
||||
r >>= 16 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask16(r);
|
||||
#else
|
||||
simde_svint16_t r;
|
||||
|
||||
uint_fast64_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(uint_fast64_t, op2) - HEDLEY_STATIC_CAST(uint_fast64_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcnth()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~UINT16_C(0) : UINT16_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint16(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b16_u64
|
||||
#define svwhilelt_b16_u64(op1, op2) simde_svwhilelt_b16_u64(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b32_u64(uint64_t op1, uint64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b32_u64(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask16(HEDLEY_STATIC_CAST(__mmask16, 0));
|
||||
|
||||
uint_fast64_t remaining = (HEDLEY_STATIC_CAST(uint_fast64_t, op2) - HEDLEY_STATIC_CAST(uint_fast64_t, op1));
|
||||
__mmask16 r = HEDLEY_STATIC_CAST(__mmask16, ~UINT16_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 16)) {
|
||||
r >>= 16 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask16(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask8(HEDLEY_STATIC_CAST(__mmask8, 0));
|
||||
|
||||
uint_fast64_t remaining = (HEDLEY_STATIC_CAST(uint_fast64_t, op2) - HEDLEY_STATIC_CAST(uint_fast64_t, op1));
|
||||
__mmask8 r = HEDLEY_STATIC_CAST(__mmask8, ~UINT8_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 8)) {
|
||||
r >>= 8 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask8(r);
|
||||
#else
|
||||
simde_svuint64_t r;
|
||||
|
||||
uint_fast64_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(uint_fast64_t, op2) - HEDLEY_STATIC_CAST(uint_fast64_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntw()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~UINT64_C(0) : UINT64_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svuint64(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b32_u64
|
||||
#define svwhilelt_b32_u64(op1, op2) simde_svwhilelt_b32_u64(op1, op2)
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_svbool_t
|
||||
simde_svwhilelt_b64_u64(uint64_t op1, uint64_t op2) {
|
||||
#if defined(SIMDE_ARM_SVE_NATIVE)
|
||||
return svwhilelt_b64_u64(op1, op2);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && (SIMDE_ARM_SVE_VECTOR_SIZE >= 512) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask8(HEDLEY_STATIC_CAST(__mmask8, 0));
|
||||
|
||||
uint_fast64_t remaining = (HEDLEY_STATIC_CAST(uint_fast64_t, op2) - HEDLEY_STATIC_CAST(uint_fast64_t, op1));
|
||||
__mmask8 r = HEDLEY_STATIC_CAST(__mmask8, ~UINT8_C(0));
|
||||
if (HEDLEY_UNLIKELY(remaining < 8)) {
|
||||
r >>= 8 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask8(r);
|
||||
#elif defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE) \
|
||||
&& (!defined(HEDLEY_MSVC_VERSION) || HEDLEY_MSVC_VERSION_CHECK(19,20,0))
|
||||
if (HEDLEY_UNLIKELY(op1 >= op2))
|
||||
return simde_svbool_from_mmask4(HEDLEY_STATIC_CAST(__mmask8, 0));
|
||||
|
||||
uint_fast64_t remaining = (HEDLEY_STATIC_CAST(uint_fast64_t, op2) - HEDLEY_STATIC_CAST(uint_fast64_t, op1));
|
||||
__mmask8 r = HEDLEY_STATIC_CAST(__mmask8, 0x0f);
|
||||
if (HEDLEY_UNLIKELY(remaining < 4)) {
|
||||
r >>= 4 - remaining;
|
||||
}
|
||||
|
||||
return simde_svbool_from_mmask4(r);
|
||||
#else
|
||||
simde_svint64_t r;
|
||||
|
||||
uint_fast64_t remaining = (op1 >= op2) ? 0 : (HEDLEY_STATIC_CAST(uint_fast64_t, op2) - HEDLEY_STATIC_CAST(uint_fast64_t, op1));
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (int i = 0 ; i < HEDLEY_STATIC_CAST(int, simde_svcntd()) ; i++) {
|
||||
r.values[i] = (remaining-- > 0) ? ~INT64_C(0) : INT64_C(0);
|
||||
}
|
||||
|
||||
return simde_svbool_from_svint64(r);
|
||||
#endif
|
||||
}
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef simde_svwhilelt_b64_u64
|
||||
#define svwhilelt_b64_u64(op1, op2) simde_svwhilelt_b64_u64(op1, op2)
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b8 ( int32_t op1, int32_t op2) { return simde_svwhilelt_b8_s32(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b8 ( int64_t op1, int64_t op2) { return simde_svwhilelt_b8_s64(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b8 (uint32_t op1, uint32_t op2) { return simde_svwhilelt_b8_u32(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b8 (uint64_t op1, uint64_t op2) { return simde_svwhilelt_b8_u64(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b16( int32_t op1, int32_t op2) { return simde_svwhilelt_b16_s32(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b16( int64_t op1, int64_t op2) { return simde_svwhilelt_b16_s64(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b16(uint32_t op1, uint32_t op2) { return simde_svwhilelt_b16_u32(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b16(uint64_t op1, uint64_t op2) { return simde_svwhilelt_b16_u64(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b32( int32_t op1, int32_t op2) { return simde_svwhilelt_b32_s32(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b32( int64_t op1, int64_t op2) { return simde_svwhilelt_b32_s64(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b32(uint32_t op1, uint32_t op2) { return simde_svwhilelt_b32_u32(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b32(uint64_t op1, uint64_t op2) { return simde_svwhilelt_b32_u64(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b64( int32_t op1, int32_t op2) { return simde_svwhilelt_b64_s32(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b64( int64_t op1, int64_t op2) { return simde_svwhilelt_b64_s64(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b64(uint32_t op1, uint32_t op2) { return simde_svwhilelt_b64_u32(op1, op2); }
|
||||
SIMDE_FUNCTION_ATTRIBUTES simde_svbool_t simde_svwhilelt_b64(uint64_t op1, uint64_t op2) { return simde_svwhilelt_b64_u64(op1, op2); }
|
||||
#elif defined(SIMDE_GENERIC_)
|
||||
#define simde_svwhilelt_b8(op1, op2) \
|
||||
(SIMDE_GENERIC_((op1), \
|
||||
int32_t: simde_svwhilelt_b8_s32, \
|
||||
uint32_t: simde_svwhilelt_b8_u32, \
|
||||
int64_t: simde_svwhilelt_b8_s64, \
|
||||
uint64_t: simde_svwhilelt_b8_u64)((op1), (op2)))
|
||||
#define simde_svwhilelt_b16(op1, op2) \
|
||||
(SIMDE_GENERIC_((op1), \
|
||||
int32_t: simde_svwhilelt_b16_s32, \
|
||||
uint32_t: simde_svwhilelt_b16_u32, \
|
||||
int64_t: simde_svwhilelt_b16_s64, \
|
||||
uint64_t: simde_svwhilelt_b16_u64)((op1), (op2)))
|
||||
#define simde_svwhilelt_b32(op1, op2) \
|
||||
(SIMDE_GENERIC_((op1), \
|
||||
int32_t: simde_svwhilelt_b32_s32, \
|
||||
uint32_t: simde_svwhilelt_b32_u32, \
|
||||
int64_t: simde_svwhilelt_b32_s64, \
|
||||
uint64_t: simde_svwhilelt_b32_u64)((op1), (op2)))
|
||||
#define simde_svwhilelt_b64(op1, op2) \
|
||||
(SIMDE_GENERIC_((op1), \
|
||||
int32_t: simde_svwhilelt_b64_s32, \
|
||||
uint32_t: simde_svwhilelt_b64_u32, \
|
||||
int64_t: simde_svwhilelt_b64_s64, \
|
||||
uint64_t: simde_svwhilelt_b64_u64)((op1), (op2)))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_SVE_ENABLE_NATIVE_ALIASES)
|
||||
#undef svwhilelt_b8
|
||||
#undef svwhilelt_b16
|
||||
#undef svwhilelt_b32
|
||||
#undef svwhilelt_b64
|
||||
#define svwhilelt_b8(op1, op2) simde_svwhilelt_b8((op1), (op2))
|
||||
#define svwhilelt_b16(op1, op2) simde_svwhilelt_b16((op1), (op2))
|
||||
#define svwhilelt_b32(op1, op2) simde_svwhilelt_b32((op1), (op2))
|
||||
#define svwhilelt_b64(op1, op2) simde_svwhilelt_b64((op1), (op2))
|
||||
#endif
|
||||
|
||||
HEDLEY_DIAGNOSTIC_POP
|
||||
|
||||
#endif /* SIMDE_ARM_SVE_WHILELT_H */
|
||||
Reference in New Issue
Block a user