SuperTuxKart 1.5 upstream source (from official release tarball)
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Benjamin
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/* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Copyright:
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* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
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*/
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#if !defined(SIMDE_ARM_NEON_SM3_H)
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#define SIMDE_ARM_NEON_SM3_H
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#include "types.h"
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HEDLEY_DIAGNOSTIC_PUSH
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SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
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SIMDE_BEGIN_DECLS_
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#define ROR32(operand, shift) (((operand) >> (shift)) | ((operand) << (32-shift)))
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#define ROL32(operand, shift) (((operand) >> (32-shift)) | ((operand) << (shift)))
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#define LSR(operand, shift) ((operand) >> (shift))
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#define LSL(operand, shift) ((operand) << (shift))
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SIMDE_FUNCTION_ATTRIBUTES
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simde_uint32x4_t
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simde_vsm3ss1q_u32(simde_uint32x4_t n, simde_uint32x4_t m, simde_uint32x4_t a) {
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#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_SM3)
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return vsm3ss1q_u32(n, m, a);
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#else
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simde_uint32x4_private
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r_,
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n_ = simde_uint32x4_to_private(n),
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m_ = simde_uint32x4_to_private(m),
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a_ = simde_uint32x4_to_private(a);
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r_.values[3] = ROL32((ROL32(n_.values[3], 12) + m_.values[3] + a_.values[3]), 7);
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r_.values[2] = 0;
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r_.values[1] = 0;
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r_.values[0] = 0;
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return simde_uint32x4_from_private(r_);
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#endif
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}
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#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
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#undef vsm3ss1q_u32
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#define vsm3ss1q_u32(n, m, a) simde_vsm3ss1q_u32((n), (m), (a))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_uint32x4_t
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simde_vsm3tt1aq_u32(simde_uint32x4_t a, simde_uint32x4_t b, simde_uint32x4_t c, const int imm2)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm2, 0, 3)
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{
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simde_uint32x4_private
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r_,
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a_ = simde_uint32x4_to_private(a),
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b_ = simde_uint32x4_to_private(b),
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c_ = simde_uint32x4_to_private(c);
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uint32_t WjPrime, TT1, SS2;
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WjPrime = c_.values[imm2];
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SS2 = b_.values[3] ^ ROL32(a_.values[3], 12);
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TT1 = a_.values[1] ^ (a_.values[3] ^ a_.values[2]);
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TT1 = (TT1 + a_.values[0] + SS2 + WjPrime);
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r_.values[0] = a_.values[1];
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r_.values[1] = ROL32(a_.values[2], 9);
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r_.values[2] = a_.values[3];
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r_.values[3] = TT1;
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return simde_uint32x4_from_private(r_);
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}
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#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_SM3)
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#define simde_vsm3tt1aq_u32(a, b, c, imm2) vsm3tt1aq_u32((a), (b), (c), (imm2));
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#endif
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#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
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#undef vsm3tt1aq_u32
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#define vsm3tt1aq_u32(a, b, c, imm2) simde_vsm3tt1aq_u32((a), (b), (c), (imm2))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_uint32x4_t
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simde_vsm3tt1bq_u32(simde_uint32x4_t a, simde_uint32x4_t b, simde_uint32x4_t c, const int imm2)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm2, 0, 3)
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{
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simde_uint32x4_private
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r_,
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a_ = simde_uint32x4_to_private(a),
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b_ = simde_uint32x4_to_private(b),
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c_ = simde_uint32x4_to_private(c);
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uint32_t WjPrime, TT1, SS2;
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WjPrime = c_.values[imm2];
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SS2 = b_.values[3] ^ ROL32(a_.values[3], 12);
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TT1 = (a_.values[3] & a_.values[1]) | (a_.values[3] & a_.values[2]) | (a_.values[1] & a_.values[2]);
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TT1 = (TT1 + a_.values[0] + SS2 + WjPrime);
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r_.values[0] = a_.values[1];
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r_.values[1] = ROL32(a_.values[2], 9);
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r_.values[2] = a_.values[3];
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r_.values[3] = TT1;
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return simde_uint32x4_from_private(r_);
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}
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#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_SM3)
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#define simde_vsm3tt1bq_u32(a, b, c, imm2) vsm3tt1bq_u32((a), (b), (c), (imm2));
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#endif
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#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
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#undef vsm3tt1bq_u32
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#define vsm3tt1bq_u32(a, b, c, imm2) simde_vsm3tt1bq_u32((a), (b), (c), (imm2))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_uint32x4_t
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simde_vsm3tt2aq_u32(simde_uint32x4_t a, simde_uint32x4_t b, simde_uint32x4_t c, const int imm2)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm2, 0, 3)
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{
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simde_uint32x4_private
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r_,
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a_ = simde_uint32x4_to_private(a),
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b_ = simde_uint32x4_to_private(b),
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c_ = simde_uint32x4_to_private(c);
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uint32_t Wj, TT2;
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Wj = c_.values[imm2];
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TT2 = a_.values[1] ^ (a_.values[3] ^ a_.values[2]);
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TT2 = (TT2 + a_.values[0] + b_.values[3] + Wj);
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r_.values[0] = a_.values[1];
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r_.values[1] = ROL32(a_.values[2], 19);
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r_.values[2] = a_.values[3];
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r_.values[3] = TT2 ^ ROL32(TT2, 9) ^ ROL32(TT2, 17);
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return simde_uint32x4_from_private(r_);
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}
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#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_SM3)
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#define simde_vsm3tt2aq_u32(a, b, c, imm2) vsm3tt2aq_u32((a), (b), (c), (imm2));
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#endif
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#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
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#undef vsm3tt2aq_u32
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#define vsm3tt2aq_u32(a, b, c, imm2) simde_vsm3tt2aq_u32((a), (b), (c), (imm2))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_uint32x4_t
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simde_vsm3tt2bq_u32(simde_uint32x4_t a, simde_uint32x4_t b, simde_uint32x4_t c, const int imm2)
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SIMDE_REQUIRE_CONSTANT_RANGE(imm2, 0, 3)
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{
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simde_uint32x4_private
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r_,
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a_ = simde_uint32x4_to_private(a),
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b_ = simde_uint32x4_to_private(b),
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c_ = simde_uint32x4_to_private(c);
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uint32_t Wj, TT2;
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Wj = c_.values[imm2];
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TT2 = (a_.values[3] & a_.values[2]) | (~(a_.values[3]) & a_.values[1]);
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TT2 = (TT2 + a_.values[0] + b_.values[3] + Wj);
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r_.values[0] = a_.values[1];
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r_.values[1] = ROL32(a_.values[2], 19);
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r_.values[2] = a_.values[3];
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r_.values[3] = TT2 ^ ROL32(TT2, 9) ^ ROL32(TT2, 17);
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return simde_uint32x4_from_private(r_);
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}
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#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_SM3)
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#define simde_vsm3tt2bq_u32(a, b, c, imm2) vsm3tt2bq_u32((a), (b), (c), (imm2));
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#endif
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#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
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#undef vsm3tt2bq_u32
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#define vsm3tt2bq_u32(a, b, c, imm2) simde_vsm3tt2bq_u32((a), (b), (c), (imm2))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_uint32x4_t
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simde_vsm3partw1q_u32(simde_uint32x4_t a, simde_uint32x4_t b, simde_uint32x4_t c) {
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#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_SM3)
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return vsm3partw1q_u32(a, b, c);
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#else
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simde_uint32x4_private
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r_,
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a_ = simde_uint32x4_to_private(a),
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b_ = simde_uint32x4_to_private(b),
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c_ = simde_uint32x4_to_private(c);
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r_.values[2] = (a_.values[2] ^ b_.values[2]) ^ (ROL32(c_.values[3], 15));
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r_.values[1] = (a_.values[1] ^ b_.values[1]) ^ (ROL32(c_.values[2], 15));
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r_.values[0] = (a_.values[0] ^ b_.values[0]) ^ (ROL32(c_.values[1], 15));
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for(int i = 0; i < 4; ++i) {
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if (i == 3) {
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r_.values[3] = (a_.values[3] ^ b_.values[3]) ^ (ROL32(r_.values[0], 15));
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}
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r_.values[i] = r_.values[i] ^ ROL32(r_.values[i], 15) ^ ROL32(r_.values[i], 23);
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}
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return simde_uint32x4_from_private(r_);
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#endif
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}
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#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
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#undef vsm3partw1q_u32
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#define vsm3partw1q_u32(a, b, c) simde_vsm3partw1q_u32((a), (b), (c))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_uint32x4_t
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simde_vsm3partw2q_u32(simde_uint32x4_t a, simde_uint32x4_t b, simde_uint32x4_t c) {
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#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_SM3)
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return vsm3partw2q_u32(a, b, c);
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#else
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simde_uint32x4_private
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r_,
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tmp_,
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a_ = simde_uint32x4_to_private(a),
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b_ = simde_uint32x4_to_private(b),
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c_ = simde_uint32x4_to_private(c);
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uint32_t tmp2;
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tmp_.values[3] = b_.values[3] ^ (ROL32(c_.values[3], 7));
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tmp_.values[2] = b_.values[2] ^ (ROL32(c_.values[2], 7));
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tmp_.values[1] = b_.values[1] ^ (ROL32(c_.values[1], 7));
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tmp_.values[0] = b_.values[0] ^ (ROL32(c_.values[0], 7));
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r_.values[3] = a_.values[3] ^ tmp_.values[3];
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r_.values[2] = a_.values[2] ^ tmp_.values[2];
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r_.values[1] = a_.values[1] ^ tmp_.values[1];
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r_.values[0] = a_.values[0] ^ tmp_.values[0];
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tmp2 = ROL32(tmp_.values[0], 15);
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tmp2 = tmp2 ^ ROL32(tmp2, 15) ^ ROL32(tmp2, 23);
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r_.values[3] = r_.values[3] ^ tmp2;
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return simde_uint32x4_from_private(r_);
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#endif
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}
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#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
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#undef vsm3partw2q_u32
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#define vsm3partw2q_u32(a, b, c) simde_vsm3partw2q_u32((a), (b), (c))
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#endif
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#undef ROR32
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#undef ROL32
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#undef LSR
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#undef LSL
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SIMDE_END_DECLS_
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HEDLEY_DIAGNOSTIC_POP
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#endif /* !defined(SIMDE_ARM_NEON_SM3_H) */
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