SuperTuxKart 1.5 upstream source (from official release tarball)
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Benjamin
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/* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Copyright:
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* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
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*/
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#if !defined(SIMDE_ARM_NEON_SHA256_H)
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#define SIMDE_ARM_NEON_SHA256_H
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#include "types.h"
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HEDLEY_DIAGNOSTIC_PUSH
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SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
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SIMDE_BEGIN_DECLS_
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#define ROR32(operand, shift) (((operand) >> (shift)) | ((operand) << (32-shift)))
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#define ROL32(operand, shift) (((operand) >> (32-shift)) | ((operand) << (shift)))
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#define LSR(operand, shift) ((operand) >> (shift))
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#define LSL(operand, shift) ((operand) << (shift))
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static uint32_t simde_SHAchoose(uint32_t x, uint32_t y, uint32_t z) {
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return (((y ^ z) & x) ^ z);
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}
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static uint32_t simde_SHAmajority(uint32_t x, uint32_t y, uint32_t z) {
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return ((x & y) | ((x | y) & z));
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}
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static uint32_t simde_SHAhashSIGMA0(uint32_t x) {
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return ROR32(x, 2) ^ ROR32(x, 13) ^ ROR32(x, 22);
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}
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static uint32_t simde_SHAhashSIGMA1(uint32_t x) {
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return ROR32(x, 6) ^ ROR32(x, 11) ^ ROR32(x, 25);
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}
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static simde_uint32x4_t
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x_simde_sha256hash(simde_uint32x4_t x, simde_uint32x4_t y, simde_uint32x4_t w, int part1) {
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uint32_t chs, maj, t;
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simde_uint32x4_private
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x_ = simde_uint32x4_to_private(x),
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y_ = simde_uint32x4_to_private(y),
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w_ = simde_uint32x4_to_private(w);
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for(int i = 0; i < 4; ++i) {
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chs = simde_SHAchoose(y_.values[0], y_.values[1], y_.values[2]);
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maj = simde_SHAmajority(x_.values[0], x_.values[1], x_.values[2]);
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t = y_.values[3] + simde_SHAhashSIGMA1(y_.values[0]) + chs + w_.values[i];
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x_.values[3] = t + x_.values[3];
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y_.values[3] = t + simde_SHAhashSIGMA0(x_.values[0]) + maj;
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uint32_t tmp = y_.values[3];
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y_.values[3] = 0x0 | y_.values[2];
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y_.values[2] = 0x0 | y_.values[1];
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y_.values[1] = 0x0 | y_.values[0];
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y_.values[0] = 0x0 | x_.values[3];
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x_.values[3] = 0x0 | x_.values[2];
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x_.values[2] = 0x0 | x_.values[1];
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x_.values[1] = 0x0 | x_.values[0];
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x_.values[0] = tmp | 0x0;
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}
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return (part1 == 1) ? simde_uint32x4_from_private(x_) : simde_uint32x4_from_private(y_);
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}
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SIMDE_FUNCTION_ATTRIBUTES
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simde_uint32x4_t
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simde_vsha256hq_u32(simde_uint32x4_t hash_efgh, simde_uint32x4_t hash_abcd, simde_uint32x4_t wk) {
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#if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARCH_ARM_SHA2)
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return vsha256hq_u32(hash_efgh, hash_abcd, wk);
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#else
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return x_simde_sha256hash(hash_efgh, hash_abcd, wk, 1);
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#endif
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}
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#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
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#undef vsha256hq_u32
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#define vsha256hq_u32(hash_efgh, hash_abcd, wk) simde_vsha256hq_u32((hash_efgh), (hash_abcd), (wk))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_uint32x4_t
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simde_vsha256h2q_u32(simde_uint32x4_t hash_efgh, simde_uint32x4_t hash_abcd, simde_uint32x4_t wk) {
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#if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARCH_ARM_SHA2)
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return vsha256h2q_u32(hash_efgh, hash_abcd, wk);
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#else
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return x_simde_sha256hash(hash_abcd, hash_efgh, wk, 0);
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#endif
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}
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#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
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#undef vsha256h2q_u32
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#define vsha256h2q_u32(hash_efgh, hash_abcd, wk) simde_vsha256h2q_u32((hash_efgh), (hash_abcd), (wk))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_uint32x4_t
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simde_vsha256su0q_u32(simde_uint32x4_t w0_3, simde_uint32x4_t w4_7) {
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#if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARCH_ARM_SHA2)
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return vsha256su0q_u32(w0_3, w4_7);
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#else
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simde_uint32x4_private
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r_,
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T_,
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x_ = simde_uint32x4_to_private(w0_3),
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y_ = simde_uint32x4_to_private(w4_7);
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T_.values[3] = y_.values[0];
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T_.values[2] = x_.values[3];
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T_.values[1] = x_.values[2];
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T_.values[0] = x_.values[1];
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uint32_t elt;
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for(int i = 0; i < 4; ++i) {
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elt = T_.values[i];
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elt = ROR32(elt, 7) ^ ROR32(elt, 18) ^ LSR(elt, 3);
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r_.values[i] = elt + x_.values[i];
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}
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return simde_uint32x4_from_private(r_);
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#endif
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}
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#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
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#undef vsha256su0q_u32
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#define vsha256su0q_u32(w0_3, w4_7) simde_vsha256su0q_u32((w0_3), (w4_7))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_uint32x4_t
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simde_vsha256su1q_u32(simde_uint32x4_t tw0_3, simde_uint32x4_t w8_11, simde_uint32x4_t w12_15) {
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#if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARCH_ARM_SHA2)
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return vsha256su1q_u32(tw0_3, w8_11, w12_15);
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#else
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simde_uint32x4_private
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r_,
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T0_,
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x_ = simde_uint32x4_to_private(tw0_3),
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y_ = simde_uint32x4_to_private(w8_11),
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z_ = simde_uint32x4_to_private(w12_15);
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simde_uint32x2_private T1_;
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T0_.values[3] = z_.values[0];
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T0_.values[2] = y_.values[3];
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T0_.values[1] = y_.values[2];
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T0_.values[0] = y_.values[1];
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uint32_t elt;
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T1_.values[1] = z_.values[3];
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T1_.values[0] = z_.values[2];
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for(int i = 0; i < 2; ++i) {
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elt = T1_.values[i];
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elt = ROR32(elt, 17) ^ ROR32(elt, 19) ^ LSR(elt, 10);
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elt = elt + x_.values[i] + T0_.values[i];
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r_.values[i] = elt;
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}
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T1_.values[1] = r_.values[1];
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T1_.values[0] = r_.values[0];
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for(int i = 2; i < 4; ++i) {
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elt = T1_.values[i-2];
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elt = ROR32(elt, 17) ^ ROR32(elt, 19) ^ LSR(elt, 10);
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elt = elt + x_.values[i] + T0_.values[i];
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r_.values[i] = elt;
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}
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return simde_uint32x4_from_private(r_);
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#endif
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}
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#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
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#undef vsha256su1q_u32
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#define vsha256su1q_u32(tw0_3, w8_11, w12_15) simde_vsha256su1q_u32((tw0_3), (w8_11), (w12_15))
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#endif
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#undef ROR32
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#undef ROL32
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#undef LSR
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#undef LSL
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SIMDE_END_DECLS_
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HEDLEY_DIAGNOSTIC_POP
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#endif /* !defined(SIMDE_ARM_NEON_SHA256_H) */
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