SuperTuxKart 1.5 upstream source (from official release tarball)
This commit is contained in:
Benjamin
@@ -0,0 +1,928 @@
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/* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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||||
* furnished to do so, subject to the following conditions:
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*
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||||
* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Copyright:
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* 2020 Evan Nemerson <evan@nemerson.com>
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* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
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* 2023 Yung-Cheng Su <eric20607@gapp.nthu.edu.tw>
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*/
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#if !defined(SIMDE_ARM_NEON_MUL_LANE_H)
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#define SIMDE_ARM_NEON_MUL_LANE_H
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#include "types.h"
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#include "mul.h"
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HEDLEY_DIAGNOSTIC_PUSH
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SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
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SIMDE_BEGIN_DECLS_
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SIMDE_FUNCTION_ATTRIBUTES
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simde_float16_t
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simde_vmulh_lane_f16(simde_float16_t a, simde_float16x4_t b, const int lane)
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SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 3) {
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return simde_vmulh_f16(a, simde_float16x4_to_private(b).values[lane]);
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}
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#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
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#if defined(__clang__) && !SIMDE_DETECT_CLANG_VERSION_CHECK(11,0,0)
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#define simde_vmulh_lane_f16(a, b, lane) \
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SIMDE_DISABLE_DIAGNOSTIC_EXPR_(SIMDE_DIAGNOSTIC_DISABLE_VECTOR_CONVERSION_, vmulh_lane_f16(a, b, lane))
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#else
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#define simde_vmulh_lane_f16(a, b, lane) vmulh_lane_f16((a), (b), (lane))
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#endif
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#endif
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#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
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#undef vmulh_lane_f16
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#define vmulh_lane_f16(a, b, lane) simde_vmulh_lane_f16(a, b, lane)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_float64_t
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simde_vmuld_lane_f64(simde_float64_t a, simde_float64x1_t b, const int lane)
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SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 0) {
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return a * simde_float64x1_to_private(b).values[lane];
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}
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#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
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#if defined(__clang__) && !SIMDE_DETECT_CLANG_VERSION_CHECK(11,0,0)
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#define simde_vmuld_lane_f64(a, b, lane) \
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SIMDE_DISABLE_DIAGNOSTIC_EXPR_(SIMDE_DIAGNOSTIC_DISABLE_VECTOR_CONVERSION_, vmuld_lane_f64(a, b, lane))
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#else
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#define simde_vmuld_lane_f64(a, b, lane) vmuld_lane_f64((a), (b), (lane))
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#endif
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#endif
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#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
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#undef vmuld_lane_f64
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#define vmuld_lane_f64(a, b, lane) simde_vmuld_lane_f64(a, b, lane)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_float64_t
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simde_vmuld_laneq_f64(simde_float64_t a, simde_float64x2_t b, const int lane)
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SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 1) {
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return a * simde_float64x2_to_private(b).values[lane];
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}
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#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
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#if defined(__clang__) && !SIMDE_DETECT_CLANG_VERSION_CHECK(11,0,0)
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#define simde_vmuld_laneq_f64(a, b, lane) \
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SIMDE_DISABLE_DIAGNOSTIC_EXPR_(SIMDE_DIAGNOSTIC_DISABLE_VECTOR_CONVERSION_, vmuld_laneq_f64(a, b, lane))
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#else
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#define simde_vmuld_laneq_f64(a, b, lane) vmuld_laneq_f64((a), (b), (lane))
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#endif
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#endif
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#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
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#undef vmuld_laneq_f64
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#define vmuld_laneq_f64(a, b, lane) simde_vmuld_laneq_f64(a, b, lane)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_float32_t
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simde_vmuls_lane_f32(simde_float32_t a, simde_float32x2_t b, const int lane)
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SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 1) {
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return a * simde_float32x2_to_private(b).values[lane];
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}
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#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
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#if defined(__clang__) && !SIMDE_DETECT_CLANG_VERSION_CHECK(11,0,0)
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#define simde_vmuls_lane_f32(a, b, lane) \
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SIMDE_DISABLE_DIAGNOSTIC_EXPR_(SIMDE_DIAGNOSTIC_DISABLE_VECTOR_CONVERSION_, vmuls_lane_f32(a, b, lane))
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#else
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#define simde_vmuls_lane_f32(a, b, lane) vmuls_lane_f32((a), (b), (lane))
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#endif
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#endif
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#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
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#undef vmuls_lane_f32
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#define vmuls_lane_f32(a, b, lane) simde_vmuls_lane_f32(a, b, lane)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_float16_t
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simde_vmulh_laneq_f16(simde_float16_t a, simde_float16x8_t b, const int lane)
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SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 7) {
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return simde_vmulh_f16(a, simde_float16x8_to_private(b).values[lane]);
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}
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#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
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#if defined(__clang__) && !SIMDE_DETECT_CLANG_VERSION_CHECK(11,0,0)
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#define simde_vmulh_laneq_f16(a, b, lane) \
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SIMDE_DISABLE_DIAGNOSTIC_EXPR_(SIMDE_DIAGNOSTIC_DISABLE_VECTOR_CONVERSION_, vmulh_laneq_f16(a, b, lane))
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#else
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#define simde_vmulh_laneq_f16(a, b, lane) vmulh_laneq_f16((a), (b), (lane))
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#endif
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#endif
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#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
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#undef vmulh_laneq_f16
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#define vmulh_laneq_f16(a, b, lane) simde_vmulh_laneq_f16(a, b, lane)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_float32_t
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simde_vmuls_laneq_f32(simde_float32_t a, simde_float32x4_t b, const int lane)
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SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 3) {
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return a * simde_float32x4_to_private(b).values[lane];
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}
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#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
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#if defined(__clang__) && !SIMDE_DETECT_CLANG_VERSION_CHECK(11,0,0)
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#define simde_vmuls_laneq_f32(a, b, lane) \
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SIMDE_DISABLE_DIAGNOSTIC_EXPR_(SIMDE_DIAGNOSTIC_DISABLE_VECTOR_CONVERSION_, vmuls_laneq_f32(a, b, lane))
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#else
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#define simde_vmuls_laneq_f32(a, b, lane) vmuls_laneq_f32((a), (b), (lane))
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#endif
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#endif
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#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
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#undef vmuls_laneq_f32
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#define vmuls_laneq_f32(a, b, lane) simde_vmuls_laneq_f32(a, b, lane)
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_float16x4_t
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simde_vmul_lane_f16(simde_float16x4_t a, simde_float16x4_t b, const int lane)
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SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 3) {
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simde_float16x4_private
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r_,
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a_ = simde_float16x4_to_private(a),
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b_ = simde_float16x4_to_private(b);
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SIMDE_VECTORIZE
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for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
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r_.values[i] = simde_vmulh_f16(a_.values[i], b_.values[lane]);
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}
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return simde_float16x4_from_private(r_);
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}
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#if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
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#define simde_vmul_lane_f16(a, b, lane) vmul_lane_f16((a), (b), (lane))
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#endif
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#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
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#undef vmul_lane_f16
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#define vmul_lane_f16(a, b, lane) simde_vmul_lane_f16((a), (b), (lane))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_float32x2_t
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simde_vmul_lane_f32(simde_float32x2_t a, simde_float32x2_t b, const int lane)
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SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 1) {
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simde_float32x2_private
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r_,
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a_ = simde_float32x2_to_private(a),
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b_ = simde_float32x2_to_private(b);
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#if defined(SIMDE_RISCV_V_NATIVE)
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r_.sv64 = __riscv_vfmul_vf_f32m1(a_.sv64, b_.values[lane], 2);
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#else
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SIMDE_VECTORIZE
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for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
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r_.values[i] = a_.values[i] * b_.values[lane];
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}
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#endif
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return simde_float32x2_from_private(r_);
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}
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#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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#define simde_vmul_lane_f32(a, b, lane) vmul_lane_f32((a), (b), (lane))
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#endif
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#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
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#undef vmul_lane_f32
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#define vmul_lane_f32(a, b, lane) simde_vmul_lane_f32((a), (b), (lane))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_float64x1_t
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simde_vmul_lane_f64(simde_float64x1_t a, simde_float64x1_t b, const int lane)
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SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 0) {
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simde_float64x1_private
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r_,
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a_ = simde_float64x1_to_private(a),
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b_ = simde_float64x1_to_private(b);
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#if defined(SIMDE_RISCV_V_NATIVE)
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r_.sv64 = __riscv_vfmul_vf_f64m1(a_.sv64, b_.values[lane], 1);
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#else
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SIMDE_VECTORIZE
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for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
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r_.values[i] = a_.values[i] * b_.values[lane];
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}
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#endif
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return simde_float64x1_from_private(r_);
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}
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#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
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#define simde_vmul_lane_f64(a, b, lane) vmul_lane_f64((a), (b), (lane))
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#endif
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#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
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#undef vmul_lane_f64
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#define vmul_lane_f64(a, b, lane) simde_vmul_lane_f64((a), (b), (lane))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
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simde_int16x4_t
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simde_vmul_lane_s16(simde_int16x4_t a, simde_int16x4_t b, const int lane)
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SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 3) {
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simde_int16x4_private
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r_,
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a_ = simde_int16x4_to_private(a),
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b_ = simde_int16x4_to_private(b);
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#if defined(SIMDE_RISCV_V_NATIVE)
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r_.sv64 = __riscv_vmul_vx_i16m1(a_.sv64, b_.values[lane], 4);
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#else
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SIMDE_VECTORIZE
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for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
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r_.values[i] = a_.values[i] * b_.values[lane];
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}
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#endif
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return simde_int16x4_from_private(r_);
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}
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#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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#define simde_vmul_lane_s16(a, b, lane) vmul_lane_s16((a), (b), (lane))
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#endif
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#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
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#undef vmul_lane_s16
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#define vmul_lane_s16(a, b, lane) simde_vmul_lane_s16((a), (b), (lane))
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#endif
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SIMDE_FUNCTION_ATTRIBUTES
|
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simde_int32x2_t
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simde_vmul_lane_s32(simde_int32x2_t a, simde_int32x2_t b, const int lane)
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SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 1) {
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simde_int32x2_private
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r_,
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a_ = simde_int32x2_to_private(a),
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b_ = simde_int32x2_to_private(b);
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#if defined(SIMDE_RISCV_V_NATIVE)
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r_.sv64 = __riscv_vmul_vx_i32m1(a_.sv64, b_.values[lane], 2);
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#else
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SIMDE_VECTORIZE
|
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for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
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r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
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#endif
|
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|
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return simde_int32x2_from_private(r_);
|
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}
|
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#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
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#define simde_vmul_lane_s32(a, b, lane) vmul_lane_s32((a), (b), (lane))
|
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#endif
|
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#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
|
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#undef vmul_lane_s32
|
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#define vmul_lane_s32(a, b, lane) simde_vmul_lane_s32((a), (b), (lane))
|
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#endif
|
||||
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||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_uint16x4_t
|
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simde_vmul_lane_u16(simde_uint16x4_t a, simde_uint16x4_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 3) {
|
||||
simde_uint16x4_private
|
||||
r_,
|
||||
a_ = simde_uint16x4_to_private(a),
|
||||
b_ = simde_uint16x4_to_private(b);
|
||||
|
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#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv64 = __riscv_vmul_vx_u16m1(a_.sv64, b_.values[lane], 4);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_uint16x4_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
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||||
#define simde_vmul_lane_u16(a, b, lane) vmul_lane_u16((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmul_lane_u16
|
||||
#define vmul_lane_u16(a, b, lane) simde_vmul_lane_u16((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_uint32x2_t
|
||||
simde_vmul_lane_u32(simde_uint32x2_t a, simde_uint32x2_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 1) {
|
||||
simde_uint32x2_private
|
||||
r_,
|
||||
a_ = simde_uint32x2_to_private(a),
|
||||
b_ = simde_uint32x2_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv64 = __riscv_vmul_vx_u32m1(a_.sv64, b_.values[lane], 2);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_uint32x2_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
#define simde_vmul_lane_u32(a, b, lane) vmul_lane_u32((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmul_lane_u32
|
||||
#define vmul_lane_u32(a, b, lane) simde_vmul_lane_u32((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_int16x4_t
|
||||
simde_vmul_laneq_s16(simde_int16x4_t a, simde_int16x8_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 7) {
|
||||
simde_int16x4_private
|
||||
r_,
|
||||
a_ = simde_int16x4_to_private(a);
|
||||
simde_int16x8_private
|
||||
b_ = simde_int16x8_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv64 = __riscv_vmul_vx_i16m1(a_.sv64, b_.values[lane], 4);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_int16x4_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
#define simde_vmul_laneq_s16(a, b, lane) vmul_laneq_s16((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmul_laneq_s16
|
||||
#define vmul_laneq_s16(a, b, lane) simde_vmul_laneq_s16((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_int32x2_t
|
||||
simde_vmul_laneq_s32(simde_int32x2_t a, simde_int32x4_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 3) {
|
||||
simde_int32x2_private
|
||||
r_,
|
||||
a_ = simde_int32x2_to_private(a);
|
||||
simde_int32x4_private
|
||||
b_ = simde_int32x4_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv64 = __riscv_vmul_vx_i32m1(a_.sv64, b_.values[lane], 2);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_int32x2_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
#define simde_vmul_laneq_s32(a, b, lane) vmul_laneq_s32((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmul_laneq_s32
|
||||
#define vmul_laneq_s32(a, b, lane) simde_vmul_laneq_s32((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_uint16x4_t
|
||||
simde_vmul_laneq_u16(simde_uint16x4_t a, simde_uint16x8_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 7) {
|
||||
simde_uint16x4_private
|
||||
r_,
|
||||
a_ = simde_uint16x4_to_private(a);
|
||||
simde_uint16x8_private
|
||||
b_ = simde_uint16x8_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv64 = __riscv_vmul_vx_u16m1(a_.sv64, b_.values[lane], 4);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_uint16x4_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
#define simde_vmul_laneq_u16(a, b, lane) vmul_laneq_u16((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmul_laneq_u16
|
||||
#define vmul_laneq_u16(a, b, lane) simde_vmul_laneq_u16((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_uint32x2_t
|
||||
simde_vmul_laneq_u32(simde_uint32x2_t a, simde_uint32x4_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 3) {
|
||||
simde_uint32x2_private
|
||||
r_,
|
||||
a_ = simde_uint32x2_to_private(a);
|
||||
simde_uint32x4_private
|
||||
b_ = simde_uint32x4_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv64 = __riscv_vmul_vx_u32m1(a_.sv64, b_.values[lane], 2);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_uint32x2_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
#define simde_vmul_laneq_u32(a, b, lane) vmul_laneq_u32((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmul_laneq_u32
|
||||
#define vmul_laneq_u32(a, b, lane) simde_vmul_laneq_u32((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_float16x8_t
|
||||
simde_vmulq_lane_f16(simde_float16x8_t a, simde_float16x4_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 3) {
|
||||
simde_float16x8_private
|
||||
r_,
|
||||
a_ = simde_float16x8_to_private(a);
|
||||
simde_float16x4_private b_ = simde_float16x4_to_private(b);
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = simde_vmulh_f16(a_.values[i], b_.values[lane]);
|
||||
}
|
||||
|
||||
return simde_float16x8_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
|
||||
#define simde_vmulq_lane_f16(a, b, lane) vmulq_lane_f16((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmulq_lane_f16
|
||||
#define vmulq_lane_f16(a, b, lane) simde_vmulq_lane_f16((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_float32x4_t
|
||||
simde_vmulq_lane_f32(simde_float32x4_t a, simde_float32x2_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 1) {
|
||||
simde_float32x4_private
|
||||
r_,
|
||||
a_ = simde_float32x4_to_private(a);
|
||||
simde_float32x2_private b_ = simde_float32x2_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv128 = __riscv_vfmul_vf_f32m1(a_.sv128, b_.values[lane], 4);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_float32x4_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
#define simde_vmulq_lane_f32(a, b, lane) vmulq_lane_f32((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmulq_lane_f32
|
||||
#define vmulq_lane_f32(a, b, lane) simde_vmulq_lane_f32((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_float64x2_t
|
||||
simde_vmulq_lane_f64(simde_float64x2_t a, simde_float64x1_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 0) {
|
||||
simde_float64x2_private
|
||||
r_,
|
||||
a_ = simde_float64x2_to_private(a);
|
||||
simde_float64x1_private b_ = simde_float64x1_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv128 = __riscv_vfmul_vf_f64m1(a_.sv128, b_.values[lane], 2);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_float64x2_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
#define simde_vmulq_lane_f64(a, b, lane) vmulq_lane_f64((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmulq_lane_f64
|
||||
#define vmulq_lane_f64(a, b, lane) simde_vmulq_lane_f64((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_int16x8_t
|
||||
simde_vmulq_lane_s16(simde_int16x8_t a, simde_int16x4_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 3) {
|
||||
simde_int16x8_private
|
||||
r_,
|
||||
a_ = simde_int16x8_to_private(a);
|
||||
simde_int16x4_private b_ = simde_int16x4_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv128 = __riscv_vmul_vx_i16m1(a_.sv128, b_.values[lane], 8);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_int16x8_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
#define simde_vmulq_lane_s16(a, b, lane) vmulq_lane_s16((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmulq_lane_s16
|
||||
#define vmulq_lane_s16(a, b, lane) simde_vmulq_lane_s16((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_int32x4_t
|
||||
simde_vmulq_lane_s32(simde_int32x4_t a, simde_int32x2_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 1) {
|
||||
simde_int32x4_private
|
||||
r_,
|
||||
a_ = simde_int32x4_to_private(a);
|
||||
simde_int32x2_private b_ = simde_int32x2_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv128 = __riscv_vmul_vx_i32m1(a_.sv128, b_.values[lane], 4);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_int32x4_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
#define simde_vmulq_lane_s32(a, b, lane) vmulq_lane_s32((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmulq_lane_s32
|
||||
#define vmulq_lane_s32(a, b, lane) simde_vmulq_lane_s32((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_uint16x8_t
|
||||
simde_vmulq_lane_u16(simde_uint16x8_t a, simde_uint16x4_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 3) {
|
||||
simde_uint16x8_private
|
||||
r_,
|
||||
a_ = simde_uint16x8_to_private(a);
|
||||
simde_uint16x4_private b_ = simde_uint16x4_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv128 = __riscv_vmul_vx_u16m1(a_.sv128, b_.values[lane], 8);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_uint16x8_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
#define simde_vmulq_lane_u16(a, b, lane) vmulq_lane_u16((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmulq_lane_u16
|
||||
#define vmulq_lane_u16(a, b, lane) simde_vmulq_lane_u16((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_uint32x4_t
|
||||
simde_vmulq_lane_u32(simde_uint32x4_t a, simde_uint32x2_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 1) {
|
||||
simde_uint32x4_private
|
||||
r_,
|
||||
a_ = simde_uint32x4_to_private(a);
|
||||
simde_uint32x2_private b_ = simde_uint32x2_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv128 = __riscv_vmul_vx_u32m1(a_.sv128, b_.values[lane], 4);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_uint32x4_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
|
||||
#define simde_vmulq_lane_u32(a, b, lane) vmulq_lane_u32((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmulq_lane_u32
|
||||
#define vmulq_lane_u32(a, b, lane) simde_vmulq_lane_u32((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_float16x8_t
|
||||
simde_vmulq_laneq_f16(simde_float16x8_t a, simde_float16x8_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 7) {
|
||||
simde_float16x8_private
|
||||
r_,
|
||||
a_ = simde_float16x8_to_private(a),
|
||||
b_ = simde_float16x8_to_private(b);
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = simde_vmulh_f16(a_.values[i], b_.values[lane]);
|
||||
}
|
||||
|
||||
return simde_float16x8_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
|
||||
#define simde_vmulq_laneq_f16(a, b, lane) vmulq_laneq_f16((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmulq_laneq_f16
|
||||
#define vmulq_laneq_f16(a, b, lane) simde_vmulq_laneq_f16((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_float32x4_t
|
||||
simde_vmulq_laneq_f32(simde_float32x4_t a, simde_float32x4_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 3) {
|
||||
simde_float32x4_private
|
||||
r_,
|
||||
a_ = simde_float32x4_to_private(a),
|
||||
b_ = simde_float32x4_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv128 = __riscv_vfmul_vf_f32m1(a_.sv128, b_.values[lane], 4);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_float32x4_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
#define simde_vmulq_laneq_f32(a, b, lane) vmulq_laneq_f32((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmulq_laneq_f32
|
||||
#define vmulq_laneq_f32(a, b, lane) simde_vmulq_laneq_f32((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_float64x2_t
|
||||
simde_vmulq_laneq_f64(simde_float64x2_t a, simde_float64x2_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 1) {
|
||||
simde_float64x2_private
|
||||
r_,
|
||||
a_ = simde_float64x2_to_private(a),
|
||||
b_ = simde_float64x2_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv128 = __riscv_vfmul_vf_f64m1(a_.sv128, b_.values[lane], 2);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_float64x2_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
#define simde_vmulq_laneq_f64(a, b, lane) vmulq_laneq_f64((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmulq_laneq_f64
|
||||
#define vmulq_laneq_f64(a, b, lane) simde_vmulq_laneq_f64((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_int16x8_t
|
||||
simde_vmulq_laneq_s16(simde_int16x8_t a, simde_int16x8_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 7) {
|
||||
simde_int16x8_private
|
||||
r_,
|
||||
a_ = simde_int16x8_to_private(a),
|
||||
b_ = simde_int16x8_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv128 = __riscv_vmul_vx_i16m1(a_.sv128, b_.values[lane], 8);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_int16x8_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
#define simde_vmulq_laneq_s16(a, b, lane) vmulq_laneq_s16((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmulq_laneq_s16
|
||||
#define vmulq_laneq_s16(a, b, lane) simde_vmulq_laneq_s16((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_int32x4_t
|
||||
simde_vmulq_laneq_s32(simde_int32x4_t a, simde_int32x4_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 3) {
|
||||
simde_int32x4_private
|
||||
r_,
|
||||
a_ = simde_int32x4_to_private(a),
|
||||
b_ = simde_int32x4_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv128 = __riscv_vmul_vx_i32m1(a_.sv128, b_.values[lane], 4);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_int32x4_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
#define simde_vmulq_laneq_s32(a, b, lane) vmulq_laneq_s32((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmulq_laneq_s32
|
||||
#define vmulq_laneq_s32(a, b, lane) simde_vmulq_laneq_s32((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_uint16x8_t
|
||||
simde_vmulq_laneq_u16(simde_uint16x8_t a, simde_uint16x8_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 7) {
|
||||
simde_uint16x8_private
|
||||
r_,
|
||||
a_ = simde_uint16x8_to_private(a),
|
||||
b_ = simde_uint16x8_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv128 = __riscv_vmul_vx_u16m1(a_.sv128, b_.values[lane], 8);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_uint16x8_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
#define simde_vmulq_laneq_u16(a, b, lane) vmulq_laneq_u16((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmulq_laneq_u16
|
||||
#define vmulq_laneq_u16(a, b, lane) simde_vmulq_laneq_u16((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_uint32x4_t
|
||||
simde_vmulq_laneq_u32(simde_uint32x4_t a, simde_uint32x4_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 3) {
|
||||
simde_uint32x4_private
|
||||
r_,
|
||||
a_ = simde_uint32x4_to_private(a),
|
||||
b_ = simde_uint32x4_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv128 = __riscv_vmul_vx_u32m1(a_.sv128, b_.values[lane], 4);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_uint32x4_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
#define simde_vmulq_laneq_u32(a, b, lane) vmulq_laneq_u32((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmulq_laneq_u32
|
||||
#define vmulq_laneq_u32(a, b, lane) simde_vmulq_laneq_u32((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_float16x4_t
|
||||
simde_vmul_laneq_f16(simde_float16x4_t a, simde_float16x8_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 7) {
|
||||
simde_float16x4_private
|
||||
r_,
|
||||
a_ = simde_float16x4_to_private(a);
|
||||
simde_float16x8_private b_ = simde_float16x8_to_private(b);
|
||||
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = simde_vmulh_f16(a_.values[i], b_.values[lane]);
|
||||
}
|
||||
|
||||
return simde_float16x4_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
|
||||
#define simde_vmul_laneq_f16(a, b, lane) vmul_laneq_f16((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmul_laneq_f16
|
||||
#define vmul_laneq_f16(a, b, lane) simde_vmul_laneq_f16((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_float32x2_t
|
||||
simde_vmul_laneq_f32(simde_float32x2_t a, simde_float32x4_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 3) {
|
||||
simde_float32x2_private
|
||||
r_,
|
||||
a_ = simde_float32x2_to_private(a);
|
||||
simde_float32x4_private b_ = simde_float32x4_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv64 = __riscv_vfmul_vf_f32m1(a_.sv64, b_.values[lane], 2);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_float32x2_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
#define simde_vmul_laneq_f32(a, b, lane) vmul_laneq_f32((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmul_laneq_f32
|
||||
#define vmul_laneq_f32(a, b, lane) simde_vmul_laneq_f32((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_FUNCTION_ATTRIBUTES
|
||||
simde_float64x1_t
|
||||
simde_vmul_laneq_f64(simde_float64x1_t a, simde_float64x2_t b, const int lane)
|
||||
SIMDE_REQUIRE_CONSTANT_RANGE(lane, 0, 1) {
|
||||
simde_float64x1_private
|
||||
r_,
|
||||
a_ = simde_float64x1_to_private(a);
|
||||
simde_float64x2_private b_ = simde_float64x2_to_private(b);
|
||||
|
||||
#if defined(SIMDE_RISCV_V_NATIVE)
|
||||
r_.sv64 = __riscv_vfmul_vf_f64m1(a_.sv64, b_.values[lane], 1);
|
||||
#else
|
||||
SIMDE_VECTORIZE
|
||||
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
|
||||
r_.values[i] = a_.values[i] * b_.values[lane];
|
||||
}
|
||||
#endif
|
||||
|
||||
return simde_float64x1_from_private(r_);
|
||||
}
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
|
||||
#define simde_vmul_laneq_f64(a, b, lane) vmul_laneq_f64((a), (b), (lane))
|
||||
#endif
|
||||
#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
|
||||
#undef vmul_laneq_f64
|
||||
#define vmul_laneq_f64(a, b, lane) simde_vmul_laneq_f64((a), (b), (lane))
|
||||
#endif
|
||||
|
||||
SIMDE_END_DECLS_
|
||||
HEDLEY_DIAGNOSTIC_POP
|
||||
|
||||
#endif /* !defined(SIMDE_ARM_NEON_MUL_LANE_H) */
|
||||
Reference in New Issue
Block a user